Data SheetAD9364Table 8. FDD Mode, 800 MHz ParameterMinTypMaxUnitTest Conditions/Comments RX AND TX 5 MHz Bandwidth 7 dBm 490 mA −27 dBm 345 mA 10 MHz Bandwidth 7 dBm 540 mA −27 dBm 395 mA 20 MHz Bandwidth 7 dBm 615 mA −27 dBm 470 mA Table 9. FDD Mode, 2.4 GHz ParameterMinTypMaxUnitTest Conditions/Comments RX AND TX 5 MHz Bandwidth 7 dBm 500 mA −27 dBm 350 mA 10 MHz Bandwidth 7 dBm 540 mA −27 dBm 390 mA 20 MHz Bandwidth 7 dBm 620 mA −27 dBm 475 mA Table 10. FDD Mode, 5.5 GHz ParameterMinTypMaxUnitTest Conditions/Comments RX AND TX 5 MHz Bandwidth 7 dBm 550 mA −27 dBm 385 mA Rev. C | Page 9 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Current Consumption—VDD_Interface Current Consumption—VDDD1P3_DIG and VDDAx (Combination of All 1.3 V Supplies) Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Frequency Band 2.4 GHz Frequency Band 5.5 GHz Frequency Band Theory of Operation General Receiver Transmitter Clock Input Options Synthesizers RF PLLs BB PLL Digital Data Interface DATA_CLK Signal FB_CLK Signal RX_FRAME Signal Enable State Machine SPI Control Mode Pin Control Mode SPI Interface Control Pins Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO Pins (GPO_3 to GPO_0) Auxiliary Converters AUXADC AUXDAC1 and AUXDAC2 Powering the AD9364 Packaging and Ordering Information Outline Dimensions Ordering Guide
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