Datasheet AD9361 (Analog Devices) - 29

Data Sheet AD9361 5.5 GHz FREQUENCY BAND 6 5 5 0 ) dB 4 ( –5 E ) R B 3 –10 FIGU E X EVM (d OIS R –40°C –40°C N +25°C 2 +25°C –15 X +85°C R +85°C 1 –20 –25 05.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0
056 053
–72 –67 –62 –57 –52 –47 –42 –37 –32 RF FREQUENCY (GHz) INTERFERER POWER LEVEL (dBm)
10453- 10453- Figure 53. RX Noise Figure vs. RF Frequency Figure 56. RX EVM vs. Interferer Power Level, WiMAX 40 MHz Signal of Interest with PIN = −74 dBm, WiMAX 40 MHz Blocker at 40 MHz Offset
5 5 4 0 3 B) –40°C –5 d 2 +25°C ) B R ( +85°C –40°C 1 –10 +25°C RRO +85°C I E X EVM (d S 0 R RS –15 –1 –20 –2 –3 –25 –90 –80 –70 –60 –50 –40 –30 –20 –10
054
–60 –55 –50 –45 –40 –35 –30 –25
057
RX INPUT POWER (dBm)
10453-
INTERFERER POWER LEVEL (dBm)
10453- Figure 54. RSSI Error vs. RX Input Power, Referenced to −50 dBm Input Power Figure 57. RX EVM vs. Interferer Power Level, WiMAX 40 MHz Signal of at 5.8 GHz Interest with PIN = −74 dBm, WiMAX 40 MHz Blocker at 80 MHz Offset
0 70 –5 –40°C 68 –10 +25°C +85°C ) –15 B B) 66 d N ( –20 AI X EVM (d G R 64 –25 RX –30 –40°C 62 +25°C +85°C –35 –40 60 –74 –68 –62 –56 –50 –44 –38 –32 –26 –20
055
5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0
058
RX INPUT POWER (dBm)
10453-
FREQUENCY (GHz)
10453- Figure 55. RX EVM vs. RX Input Power, 64 QAM WiMAX 40 MHz Mode, Figure 58. RX Gain vs. Frequency, Gain Index = 76 (Maximum Setting) 40 MHz REF_CLK (Doubled Internally for RF Synthesizer) Rev. F | Page 29 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 2.4 GHz FREQUENCY BAND 5.5 GHz FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME Signal ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT[7:0]) Control Inputs (CTRL_IN[3:0]) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9361 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE