Datasheet ADCMP609 (Analog Devices) - 5

Data Sheet ADCMP609 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VCC 1 8 Q ADCMP609 VP 2 7 Q TOP VIEW VN 3 (Not to Scale) 6 VEE S
002
DN 4 5 HYS
06918- Figure 2. ADCMP609 Pin Configuration
Table 4. ADCMP609 P in Function Descriptions Pin No. Mnemonic Description
1 VCC VCC Supply. 2 VP Noninverting Analog Input. 3 VN Inverting Analog Input. 4 SDN Shutdown. Drive this pin low to shut down the device. 5 HYS Hysteresis Control. Bias with resistor or current source for hysteresis. 6 VEE Negative Supply Voltage. 7 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input (VP) is greater than the analog voltage at the inverting input (VN), provided the comparator is in compare mode. 8 Q Inverting Output. Q is at logic low if the analog voltage at the noninverting input (VP) is greater than the analog voltage at the inverting input (VN), provided the comparator is in compare mode. Rev. C | Page 5 of 12 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING TTL-/CMOS-COMPATIBLE OUTPUT STAGE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINT MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATIONS CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE