Datasheet ADCMP608 (Analog Devices) - 10

ADCMP608 Data Sheet OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 6 5 4 2.40 1.25 2.10 1.15 1 2 3 1.80 0.65 BSC 1.30 BSC 1.00 1.10 0.40 0.90 0.80 0.10 0.70 0.46 0.22 0.10 MAX SEATING 0.30 0.36 PLANE 0.08 COPLANARITY 0.15 0.26 0.10 -A 09 COMPLIANT TO JEDEC STANDARDS MO-203-AB 728 0
Figure 14. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters
ORDERING GUIDE Package Model1 Temperature Range Package Description Option Branding
ADCMP608BKSZ-R2 −40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 G0U ADCMP608BKSZ-RL −40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 G0U ADCMP608BKSZ-REEL7 −40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 G0U EVAL-ADCMP608BKSZ Evaluation Board 1 Z = RoHS Compliant Part.
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Rev. B | Page 10 of 10 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING TTL-/CMOS-COMPATIBLE OUTPUT STAGE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION CROSSOVER BIAS POINT MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE