Datasheet ADCMP606, ADCMP607 (Analog Devices) - 13

Data Sheet ADCMP606/ADCMP607 TYPICAL APPLICATION CIRCUITS 2.5V TO 5V 5V 0.1µF 50Ω 50Ω 50Ω 50Ω INPUT 2kΩ 2kΩ ADCMP606 CML OUTPUT CML ADCMP606 PWM OUTPUT 0.1µF
018
INPUT 2.5V ±50mV
05917- Figure 19. Self-Biased, 50% Slicer on the ADCMP606
INPUT 2.5V 10kΩ REF 10kΩ 3.3V ADCMP601 50Ω 50Ω LE/HYS 10kΩ 150pF LVDS 100Ω ADCMP606 CML 100kΩ OUTPUT
022 019 05917- 05917- Figure 20. LVDS to CML on the ADCMP606 Figure 23. Oscillator and Pulse-Width Modulator on the ADCMP601 and ADCMP606
2.5V TO 5V 5V 50Ω 50Ω 10kΩ 50Ω 50Ω ADCMP607 CML 82pF ADCMP607 OUTPUT LE/HYS LE/HYS DIGITAL 74 VHC INPUT 1G07 150kΩ 10kΩ
020
CONTROL CONTROL
023
CURRENT 10kΩ
05917-
VOLTAGE 0V TO 2.5V 150kΩ
05917- Figure 21. Current-Controlled Oscillator on the ADCMP607 Figure 24. Hysteresis Adjustment with Latch on the ADCMP607
+2.5V – 3V V 3.3V CCI VCCO 1N4001 V V CCI CCO 50Ω 50Ω 50Ω 50Ω ADCMP607 OUTPUT LVDS 100Ω ADCMP607 3.3V PECL
021 024 05917-
–2.5V VEE
05917- Figure 22. Fake PECL Levels Using a Series Diode on the ADCMP607 Figure 25. Ground-Referenced CML with ±3 V Input Range on the ADCMP607 Rev. C | Page 13 of 14 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING CML-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE