Datasheet ADCMP606, ADCMP607 (Analog Devices) - 14

ADCMP606/ADCMP607 Data Sheet OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 6 5 4 2.40 1.25 2.10 1.15 1 2 3 1.80 0.65 BSC 1.30 BSC 1.00 1.10 0.40 0.90 0.80 0.10 0.70 0.46 0.22 0.10 MAX SEATING 0.30 0.36 PLANE 0.08 COPLANARITY 0.15 0.26 0.10 COMPLIANT TO JEDEC STANDARDS MO-203-AB 072809-A
Figure 26. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters
3.10 0.30 3.00 SQ 0.23 2.90 PIN 1 0.18 PIN 1 INDICATOR 10 12 INDICATOR 0.50 9 1 BSC EXPOSED 1.65 PAD 1.50 SQ 1.35 7 3 6 4 0.25 MIN 0.50 TOP VIEW 0.40 BOTTOM VIEW 0.30 0.80 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 0.75 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF A COMPLIANT TO JEDEC STANDARDS MO-220-WEED. 111808-
Figure 27. 12-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm and 0.75 mm Package Height (CP-12-5) Dimensions shown in millimeters
ORDERING GUIDE Package Model
1
Temperature Range Package Description Option Branding
ADCMP606BKSZ-R2 −40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 G0S ADCMP606BKSZ-REEL7 −40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 G0S EVAL-ADCMP606BKSZ Evaluation Board ADCMP607BCPZ-R2 −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP] CP-12-5 G0H ADCMP607BCPZ-R7 −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP] CP-12-5 G0H ADCMP607BCPZ-WP −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP] CP-12-5 G0H EVAL-ADCMP607BCPZ Evaluation Board 1 Z = RoHS Compliant Part.
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Rev. C | Page 14 of 14 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING CML-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE