Datasheet ADCMP606, ADCMP607 (Analog Devices) - 7

Data Sheet ADCMP606/ADCMP607 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Q 1 6 Q ADCMP606 VEE 2 5 TOP VIEW VCCI/VCCO (Not to Scale)
002
V
7-
P 3 4 VN
91 05 Figure 3. ADCMP606 Pin Configuration
Table 5. ADCMP606 ( 6-Lead SC70) Pin Function Descriptions Pin No. Mnemonic Description
1 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN. 2 VEE Negative Supply Voltage. 3 VP Noninverting Analog Input. 4 VN Inverting Analog Input. 5 VCCI/VCCO Input Section Supply/Output Section Supply. Shared pin. 6 Q Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VIN.
EE Q V Q 2 1 0 1 1 1 VCCO 1 9 VEE ADCMP607 VCCI 2 8 LE/HYS TOP VIEW VEE 3 7 SDN 4 5 6 P N V EE V V NOTES 1. EXPOSED PAD. IF CONNECTED, THE EPAD MUST BE CONNECTED TO VEE. THE METALLIC BACK SURFACE OF THE PACKAGE IS ELECTRICALLY CONNECTED TO VEE. IT CAN BE LEFT FLOATING BECAUSE PIN 3, PIN 5,
3
PIN 9, AND PIN 11 PROVIDE ADEQUATE ELECTRICAL CONNECTION. IT CAN
00 7-
ALSO BE SOLDERED TO THE APPLICATION BOARD IF IMPROVED THERMAL
591
AND/OR MECHANICAL STABILITY IS DESIRED.
0 Figure 4. ADCMP607 Pin Configuration
Table 6. ADCMP607 ( 12-Lead LFCSP) Pin Function Descriptions Pin No. Mnemonic Description
1 VCCO Output Section Supply. 2 VCCI Input Section Supply. 3, 5, 9, 11 VEE Negative Supply Voltage. 4 VP Noninverting Analog Input. 6 VN Inverting Analog Input. 7 SDN Shutdown. Drive this pin low to shut down the device. 8 LE/HYS Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch. 10 Q Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. 12 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. EPAD Exposed Pad. If connected, the EPAD must be connected to VEE. The metallic back surface of the package is electrically connected to VEE. It can be left floating because Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Rev. C | Page 7 of 14 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING CML-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE