Datasheet ADCMP603 (Analog Devices) - 7

Data Sheet ADCMP603 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EE Q V Q 1 12 1 10 V 1 9 V CCO EE ADCMP603 V 2 8 LE/HYS CCI TOP VIEW (Not to Scale) V 3 7 S EE DN 4 5 6 P N V EE V V NOTES 1. THE EXPOSED PAD IS ELECTRICALLY CONNECTED TO VEE. IT CAN BE LEFT FLOATING BECAUSE PIN 3, PIN 5, PIN 9, AND PIN 11 PROVIDE ADEQUATE ELECTRICAL CONNECTION.
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IT CAN ALSO BE SOLDERED TO THE APPLICATION BOARD FOR IMPROVED THERMAL AND/OR MECHANICAL STABILITY.
05915- Figure 3. ADCMP603 Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 VCCO Output Section Supply. 2 VCCI Input Section Supply. 3, 5, 9, 11 VEE Negative Supply Voltage. 4 VP Noninverting Analog Input. 6 VN Inverting Analog Input. 7 SDN Shutdown. Drive this pin low to shut down the device. 8 LE/HYS Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch. 10 Q Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. See the LE/HYS pin description (Pin 8) for more information. 12 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. See the LE pin description (Pin 8) for more information. 0 EPAD The exposed pad is electrically connected to VEE. It can be left floating because Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the application board for improved thermal and/or mechanical stability. Rev. A | Page 7 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING TTL-/CMOS-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINT MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE