Data SheetADCMP580/ADCMP581/ADCMP582TYPICAL APPLICATION CIRCUITSGNDVTP50Ω50ΩVPADCMP580CMLVPQVVNINVN ADCMP580QVTN1k50ΩΩ50Ω 021 VEE 04672- LATCH 017 INPUTS 04672- Figure 16. Zero-Crossing Detector with CML Outputs on the ADCMP580 Figure 20. Disabling the Latch Feature on the ADCMP580 VTPVPQVVPPVADCMP581RSECLN ADCMP581VVNNQVTN50Ω50Ω50Ω50Ω750ΩVTT = –2VVVTT 022 TTVEELATCH 018 04672- INPUTS 04672- Figure 17. LVDS to a 50 Ω Back-Terminated (RS) ECL Receiver on the ADCMP581 Figure 21. Disabling the Latch Feature on the ADCMP581 VPADCMP580ADCMP582RSPECLHYSVN500Ω50ΩΩ TO 5kΩ50Ω750Ω50Ω 019 023 VEEVCCOVTT = VCCO – 2V 04672- 04672- Figure 18. Adding Hysteresis Using the HYS Control on the ADCMP580 Figure 22. Disabling the Latch Feature on the ADCMP582 GND50Ω50Ω+QVINADCMP580VTH–QLATCH INPUTS 020 04672- Figure 19. Comparator with −2 to +3 V Input Range on the ADCMP580 Rev. B | Page 11 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TYPICAL APPLICATION CIRCUITS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING ADCMP580/ADCMP581/ADCMP582 FAMILY OF OUTPUT STAGES USING/DISABLING THE LATCH FEATURE OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT OUTLINE DIMENSIONS ORDERING GUIDE NOTES
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