Datasheet ADCMP580, ADCMP581, ADCMP582 (Analog Devices) - 8

link to page 9
ADCMP580/ADCMP581/ADCMP582 Data Sheet S CCI ND EE V G HY V 16 15 14 13 VTP 1 12 VCCO VP 2 11 Q ADCMP582 V 3 TOP VIEW 10 Q N VTN 4 9 VCCO 5 6 7 8 TT CCI LE LE V V NOTES 1. THE METALLIC BACK SURFACE OF THE PACKAGE IS NOT ELECTRICALLY CONNECTED TO ANY PART OF THE CIRCUIT. IT CAN BE LEFT FLOATING FOR OPTIMAL ELECTRICAL ISOLATION BETWEEN THE PACKAGE HANDLE AND THE SUBSTRATE OF THE DIE. IT CAN ALSO BE SOLDERED TO THE
004
APPLICATION BOARD IF IMPROVED THERMAL AND/OR MECHANICAL STABILITY IS DESIRED.
04672- Figure 4. ADCMP582 Pin Configuration
Table 5. ADCMP582 P in Function Descriptions Pin No. Mnemonic Description
1 VTP Termination Resistor Return Pin for VP Input. 2 VP Noninverting Analog Input. 3 VN Inverting Analog Input. 4 VTN Termination Resistor Return Pin for VN Input. 5, 16 VCCI Positive Supply Voltage. 6 LE Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input of the comparator. In latch mode (LE = high), the output reflects the input state just prior to the comparator being placed into latch mode. LE must be driven in complement with LE. 7 LE Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the input of the comparator. In latch mode (LE = low), the output reflects the input state just prior to the comparator being placed into latch mode. LE must be driven in complement with LE. 8 VTT Termination Return Pin for the LE/LE Input Pins. For the ADCMP582 (PECL output stage), connect this pin to the VCCO –2 V termination potential. 9, 12 VCCO Digital Ground Pin/Positive Logic Power Supply Terminal. This pin must be connected to the positive logic power VCCO supply. 10 Q Inverting Output. Q is logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions (Pin 6 to Pin 7) for more information. 11 Q Noninverting Output. Q is logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions (Pin 6 to Pin 7) for more information. 13 VEE Negative Power Supply. 14 HYS Hysteresis Control. Leave this pin disconnected for zero hysteresis. Connect this pin to the VEE supply with a suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 8 for proper sizing of the HYS hysteresis control resistor. 15 GND Analog Ground. EPAD Exposed Pad. The metallic back surface of the package is not electrically connected to any part of the circuit. It can be left floating for optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Rev. B | Page 8 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TYPICAL APPLICATION CIRCUITS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING ADCMP580/ADCMP581/ADCMP582 FAMILY OF OUTPUT STAGES USING/DISABLING THE LATCH FEATURE OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT OUTLINE DIMENSIONS ORDERING GUIDE NOTES