Datasheet ADCMP551, ADCMP552, ADCMP553 (Analog Devices) - 10

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ADCMP551/ADCMP552/ADCMP553 Data Sheet TIMING INFORMATION LATCH ENABLE 50% LATCH ENABLE tS tPL tH V DIFFERENTIAL IN VREF ± VOS INPUT VOLTAGE VOD tPDL tPLOH Q OUTPUT 50% tF tPDH 50% Q OUTPUT tPLOL tR
04722-016 Figure 17. System Timing Diagram Figure 17 shows the compare and latch features of the ADCMP551/ADCMP552/ADCMP553. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions Symbol Timing Description
tPDH Input to Output High Delay Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low-to-high transition tPDL Input to Output Low Delay Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high-to-low transition tPLOH Latch Enable to Output High Delay Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition tPLOL Latch Enable to Output Low Delay Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition tH Minimum Hold Time Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs tPL Minimum Latch Enable Pulse Width Minimum time the latch enable signal must be high to acquire an input signal change tS Minimum Setup Time Minimum time before the negative transition of the latch enable signal that an input signal change must be present to be acquired and held at the outputs tR Output Rise Time Amount of time required to transition from a low to a high output as measured at the 20% and 80% points tF Output Fall Time Amount of time required to transition from a high to a low output as measured at the 20% and 80% points VOD Voltage Overdrive Difference between the differential input and reference input voltages Rev. B | Page 10 of 15 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TIMING INFORMATION APPLICATIONS INFORMATION CLOCK TIMING RECOVERY OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE