Datasheet ADCMP563, ADCMP564 (Analog Devices) - 6

ADCMP563/ADCMP564 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS A A QA 1 16 QB EEV ND LE LE G QA 2 15 QB 16 15 14 13 GND 3 14 GND ADCMP563 –INA 1 12 QA LEA 4 13 LEB BRQ +INA 2 11 QA ADCMP563 LEA 5 TOP VIEW 12 LEB (Not to Scale) +INB 3 BCP 10 QB V 6 11 V TOP VIEW EE CC –INB 4 9 QB (Not to Scale) –INA 7 10 –INB +INA 8 9 +INB 5 6 7 8
04650-0-002
CC EB EB V ND L L G NOTES 1. THE EXPOSED PAD SHOULD BE EITHER CONNECTED TO VEE OR LEFT FLOATING.
Figure 5. ADCMP563 16-Lead QSOP Figure 7. ADCMP563 16-Lead LFCSP Pin Configuration Pin Configuration
GND 1 20 GND QA 2 19 QB QA 3 18 QB GND 4 ADCMP564 17 GND BRQ LEA 5 16 LEB TOP VIEW (Not to Scale) LEA 6 15 LEB V 7 14 EE VCC –INA 8 13 –INB +INA 9 12 +INB HYSA 10 11 HYSB
04650-0-012 Figure 6. ADCMP564 20-Lead QSOP Pin Configuration
Table 3. Pin Function Descriptions Pin No. ADCMP563 ADCMP563 ADCMP564 16-Lead 16-Lead 20-Lead QSOP LFCSP QSOP Mnemonic Function
1 GND Analog Ground. 1 11 2 QA One of Two Complementary Outputs for Channel A. QA is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of the LEA pin for more information. 2 12 3 QA One of Two Complementary Outputs for Channel A. QA is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of the LEA pin for more information. 3 13 4 GND Analog Ground. 4 14 5 LEA One of Two Complementary Inputs for Channel A Latch Enable. In compare mode (logic high), the output tracks change at the input of the comparator. In latch mode (logic low), the output reflects the input state just prior to the comparator being placed in the latch mode. LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to compare mode. 5 15 6 LEA One of Two Complementary Inputs for Channel A Latch Enable. In compare mode (logic low), the output tracks change at the input of the comparator. In latch mode (logic high), the output reflects the input state just prior to the Rev. D | Page 6 of 15 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TIMING INFORMATION APPLICATION INFORMATION CLOCK TIMING RECOVERY OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE