HMC874LC3C v07.0616 20 Gbps CLOCKED COMPARATORPin Descriptions Pin Number Function Description Interface Schematic 1 VTP Termination resistor return pin for INP Input. T 2 INP Non-Inverting analog input M 3 INN Inverting analog input 4 VTN Termination resistor return pin for INN input S - S 5, 16 Vcci Positive supply voltage input stage. R O 6 CLK Clock input pin, inverting side. AT R A 7 CLK Clock input pin, non-inverting side. P 8 CLKRTN Clock RTN pin, connect to GND. OM C 9, 12 Vcco Positive supply voltage for the output stage. Inverting output. Q bar is at logic low if the analog voltage at the non-inverting input, INP, is greater than the analog 10 Q voltage at the inverting input, INN, after a positive transition on CLK and negative transition on CLK. Non-inverting output. Q is at logic high if the analog voltage at the non-inverting input, INP, is greater than the analog 11 Q voltage at the inverting input, INN, after a positive transition on CLK and negative transition on CLK. Hysteresis Control pin. This pin should be left disconnected 14 HYS to minimize hysteresis. Connect to Vee with a resistor to add the desired amount of hysteresis. 13 Vee Negative power supply, -3V. 15 RTN Return for ESD protection, connect to GND. Package Base Do not DC GND. Thermal dissipation path only. For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 781-329-4700 • Order online at www.analog.com Application Support: Phone: 1-800-ANALOG-D 8 Document Outline Typical Applications Features Functional Diagram General Description Electrical Specifications Performance Characteristics Outline Drawing Package Information Evaluation PCB CLK, CLK Interfacing Resistor Network Bias Tee
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