Datasheet HMC674LC3C, HMC674LP3E (Analog Devices) - 5

Data Sheet HMC674LC3C/HMC674LP3E TIMING DESCRIPTIONS Table 6. Parameter Symbol Description
Input to Output High Delay tPDH The propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low to high transition. Input to Output Low Delay tPDL The propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high to low transition. Latch Enable (LE/LE) to Output High Delay tPLOH The propagation delay measured from the 50% point of the latch enable (LE/LE) signal high to low transition to the 50% point of an output low to high transition. Latch Enable (LE/LE) to Output Low Delay tPLOL The propagation delay measured from the 50% point of the latch enable (LE/LE) signal high to low transition to the 50% point of an output high to low transition. Minimum Hold Time tH The minimum time after the positive transition of the latch enable (LE/LE) signal that the input signal must remain unchanged to be acquired and held at the outputs. Minimum Latch Enable (LE/LE) Pulse Width tPL The minimum time that the latch enable (LE/LE) signal must be low to acquire an input signal change. Minimum Setup Time tS The minimum time before the positive transition of the latch enable (LE/LE) signal that an input signal change must be present to be acquired and held at the outputs. Output Rise Time tR The amount of time required to transition from a low to a high output as measured at the 20% and 80% points. Output Fall Time tF The amount of time required to transition from a high to a low output as measured at the 20% and 80% points. Input Overdrive Voltage VOD The difference between the input voltages (VINP and VINN).
Timing Diagram LATCH TRACK LATCH TRACK LATCH LATCH ENABLE (LE) 50% LATCH ENABLE (LE) t t PL S tH VIN DIFFERENTIAL INPUT VOLTAGE VCM ± VOS VOD tPDL tPLOH Q OUTPUT 50% tF tPDH 50% Q OUTPUT
002
tR tPLOL
14861- Figure 2. Timing Diagram Rev. K | Page 5 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LATCH ENABLE (LE/) SPECIFICATIONS DC OUTPUT SPECIFICATIONS AC SPECIFICATIONS POWER SUPPLY SPECIFICATIONS TIMING DESCRIPTIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SEQUENCING APPLICATIONS INFORMATION EVALUATION PRINTED CIRCUIT BOARD (PCB) APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE