HMC674LC3C/HMC674LP3EData SheetINTERFACE SCHEMATICSVTP,VCCOVTN50ΩINP, 005 INN 007 Q, 14861- Q 14861- Figure 5. VTP, VTN and INP, INN Interface Schematic Figure 7. Q, Q Interface Schematic VCCILE, LE 006 008 VEE 14861- HYS 14861- Figure 6. LE, LE Interface Schematic Figure 8. HYS Interface Schematic Rev. K | Page 8 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LATCH ENABLE (LE/) SPECIFICATIONS DC OUTPUT SPECIFICATIONS AC SPECIFICATIONS POWER SUPPLY SPECIFICATIONS TIMING DESCRIPTIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SEQUENCING APPLICATIONS INFORMATION EVALUATION PRINTED CIRCUIT BOARD (PCB) APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
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