Datasheet ADCMP604, ADCMP605 (Analog Devices) - 2

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ADCMP604/ADCMP605 Data Sheet TABLE OF CONTENTS
Features .. 1 Applications Information .. 10 Applications ... 1 Power/Ground Layout and Bypassing ... 10 Functional Block Diagram .. 1 LVDS-Compatible Output Stage .. 10 General Description ... 1 Using/Disabling the Latch Feature ... 10 Revision History ... 2 Optimizing Performance ... 10 Specifications ... 3 Comparator Propagation Delay Dispersion ... 11 Electrical Characteristics ... 3 Comparator Hysteresis .. 11 Timing Information ... 5 Crossover Bias Points ... 12 Absolute Maximum Ratings .. 6 Minimum Input Slew Rate Requirement .. 12 Thermal Resistance .. 6 Typical Application Circuits ... 13 ESD Caution .. 6 Outline Dimensions ... 14 Pin Configurations and Function Descriptions ... 7 Ordering Guide .. 14 Typical Performance Characteristics ... 8
REVISION HISTORY 1/15—Rev. B to Rev. C 8/07—Rev. 0 to Rev. A
Changes to Figure 4 .. 7 Changes to Features and General Description .. 1 Change to Figure 16 Caption .. 9 Changes to Electrical Characteristics Section ... 3 Updated Outline Dimensions ... 14 Changes to Table 3 ... 6 Changes to Ordering Guide .. 14 Changes to Layout ... 7 Changes to Figure 8 ... 8
11/14—Rev. A to Rev. B
Changes to Figure 14 ... 9 Changes to Figure 4 and Table 6 ... 7 Changes to Power/Ground Layout and Bypassing Section, and Changes to Figure 15 and Figure 16 ... 9 Using/Disabling the Latch Feature Section ... 10 Updated Outline Dimensions ... 14 Changes to Comparator Hysteresis Section .. 11 Changes to Ordering Guide .. 14 Changes to Crossover Bias Points Section .. 12 Changes to Ordering Guide .. 14
10/06—Revision 0: Initial Version
Rev. C | Page 2 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING LVDS-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE