Datasheet ADCMP604, ADCMP605 (Analog Devices) - 7

Data Sheet ADCMP604/ADCMP605 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Q 1 6 Q ADCMP604 VEE 2 TOP VIEW 5 VCCI/VCCO (Not to Scale)
2
V
-00
P 3 4 VN
916 05 Figure 3. ADCMP604 Pin Configuration
Table 5. ADCMP604 Pi n Function Descriptions (6-Lead SC70) Pin No. Mnemonic Description
1 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN. 2 VEE Negative Supply Voltage. 3 VP Noninverting Analog Input. 4 VN Inverting Analog Input. 5 VCCI/VCCO Input Section Supply/Output Section Supply. VCCI and VCCO are shared pin. 6 Q Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN.
E E Q V Q 2 1 0 1 1 1 V 1 9 V CCO EE ADCMP605 V 2 TOP VIEW 8 LE/HYS CCI (Not to Scale) V 3 7 S EE DN 4 5 6 P E N V E V V
3
NOTES
00
1. EXPOSED PAD. IF CONNECTED, THE
16-
EPAD MUST BE CONNECTED TO VEE.
059 Figure 4. ADCMP605 Pin Configuration
Table 6. ADCMP605 Pi n Function Descriptions (12-Lead LFCSP_WQ) Pin No. Mnemonic Description
1 VCCO Output Section Supply. 2 VCCI Input Section Supply. 3, 5, 9, 11 VEE Negative Supply Voltages. 4 VP Noninverting Analog Input. 6 VN Inverting Analog Input. 7 SDN Shutdown. Drive this pin low to shut down the device. 8 LE/HYS Latch/Hysteresis Control. Bias with resistor or current for hysteresis; drive low to latch. 10 Q Inverting Output. Q is at Logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. 12 Q Noninverting Output. Q is at Logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. Heat Sink Paddle VEE The metallic back surface of the package is electrically connected to VEE. It can be left floating because Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. EPAD Exposed Pad. If connected, the EPAD must be connected to VEE. Rev. C | Page 7 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING LVDS-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE