Datasheet ADCMP572, ADCMP573 (Analog Devices) - 8

ADCMP572/ADCMP573 Data Sheet –15.0 380 –15.5 379

A) –16.0 378 V) m NT ( –16.5 377 CURRE LEVELS ( –17.0 T 376 T BIAS TPU U –17.5 OU 375 INP –18.0 374 –18.5 373 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 –60 –40 –20 0 20 40 60 80 100 VP INPUT VOLTAGE (VN = –0.2V) TEMPERATURE (°C)
04409-044 04409-046 Figure 9. Input Bias Current vs. Input Differential Figure 12. Output Levels vs. Temperature
–16.2 496.0mV –16.3

A) –16.4 NT ( –16.5 CURRE –16.6 T BIAS U –16.7 INP –16.8 M1 –16.9–60 –40 –20 0 20 40 60 80 100 504.0mV 60.00ps/DIV
04409-049
TEMPERATURE (°C)
04409-045 Figure 10. Input Bias Current vs. Temperature Figure 13. ADCMP572 Eye Diagram at 2.5 Gbps
0.5 0.4 500.0mV 0.3 0.2 V) 0.1 m 0 OFFSET ( –0.1 –0.2 –0.3 –0.4 –0.5
04409-024
–50 –25 0 25 50 75 100 125 500.0mV 25.00ps/DIV
04409-050
TEMPERATURE ( C)
Figure 11. Input Offset Voltage vs. Temperature Figure 14. ADCMP572 Eye Diagram at 6.5 Gbps Rev. B | Page 8 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING CML/RSPECL OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATIONDELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENTS TYPICAL APPLICATION CIRCUITS TIMING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE