Datasheet ADCMP567 (Analog Devices) - 7

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Data Sheet ADCMP567 Pin No. Mnemonic Function
24 VEE Negative Supply Terminal. 25 VDD Logic Supply Terminal. 26 QA One of two complementary outputs for Channel A. QA will be at logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEA description (Pin 30) for more information. 27 QA One of two complementary outputs for Channel A. QA will be at logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEA description (Pin 30) for more information. 28 VDD Logic Supply Terminal. 29 NC No Connect. Do not connect to this pin. 30 LEA One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic high), the output will track changes at the input of the comparator. In the latch mode (logic low), the output will reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. 31 LEA One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic low), the output will track changes at the input of the comparator. In the latch mode (logic high), the output will reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. 32 GND Analog Ground. EPAD Exposed Pad. The recommended connection for the exposed pad is ground. Rev. A | Page 7 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TIMING INFORMATION APPLICATIONS INFORMATION CLOCK TIMING RECOVERY OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE