AD8611/AD8612Data SheetPIN CONFIGURATIONS AND FUNCTION DESCRIPTIONSV+ 18QAIN+ 2AD86117QAIN– 36TOP VIEWGND 001 V–(Not to Scale)45LATCH 06010- Figure 4. 8-Lead Narrow Body SOIC Pin Configuration V+ 18QAIN+AD861127QATOP VIEWIN– 36GND(Not to Scale) 002 V– 45LATCH 06010- Figure 5. 8-Lead MSOP Pin Configuration QA114QBQA213 QBGND3AD861212GNDTOP VIEWLEA411LEB(Not to Scale)V–510V+INA–69INB– 003 INA+78INB+ 06010- Figure 6. 14-Lead TSSOP Pin Configuration Table 5. Pin Function DescriptionsPin No.SOIC and MSOPTSSOPMnemonicDescription 1 10 V+ Positive Supply Terminal. 2 IN+ Noninverting Analog Input of the Differential Input Stage. 3 IN− Inverting Analog Input of the Differential Input Stage. 4 5 V− Negative Supply Terminal. 5 LATCH Latch Enable Input. 6 3, 12 GND Negative Logic Supply 7 1 QA One of Two Complementary Output for Channel A. 8 2 QA One of Two Complementary Output for Channel A. 14 QB One of Two Complementary Output for Channel B. 13 QB One of Two Complementary Output for Channel B. 4 LEA Channel A Latch Enable. 11 LEB Channel B Latch Enable. 7 INA+ Noninverting Analog Input of the Differential Input Stage for Channel A. 6 INA− Inverting Analog Input of the Differential Input Stage for Channel A. 8 INB+ Noninverting Analog Input of the Differential Input Stage for Channel B. 9 INB− Inverting Analog Input of the Differential Input Stage for Channel B. Rev. B | Page 6 of 20 Document Outline FEATURES APPLICATIONS PIN CONFIGURATIONS GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION OPTIMIZING HIGH SPEED PERFORMANCE UPGRADING THE LT1394 AND LT1016 MAXIMUM INPUT FREQUENCY AND OVERDRIVE OUTPUT LOADING CONSIDERATIONS USING THE LATCHTO MAINTAIN A CONSTANT OUTPUT INPUT STAGE AND BIAS CURRENTS USING HYSTERESIS CLOCK TIMING RECOVERY A 5 V, HIGH SPEED WINDOW COMPARATOR OUTLINE DIMENSIONS ORDERING GUIDE
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