Datasheet AD8561 (Analog Devices) - 9

AD8561 SPICE Model * AD8561 SPICE Macro-Model Typical Values * 4/98, Ver. 1.0 * TAM / ADSC * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | Latch * | | | | | DGND * | | | | | | Q * | | | | | | | QNOT * | | | | | | | | .SUBCKT AD8561 1 2 99 50 80 51 45 65 * * INPUT STAGE * * Q1 4 3 5 PIX Q2 6 2 5 PIX IBIAS 99 5 800E-6 RC1 4 50 1E3 RC2 6 50 1E3 CL1 4 6 1E-12 CIN 1 2 3E-12 VCM1 99 7 1 D1 5 7 DX EOS 3 1 POLY(1) (31,98) 1E-3 1 * * Reference Voltage * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 RREF 98 0 100E3 * * CMRR=80dB, ZERO AT 1kHz * ECM1 30 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 RCM1 30 31 10E3 RCM2 31 98 1 CCM1 30 31 15.9E-9 * * Latch Section * RX 80 51 100E3 E1 10 98 (4,6) 1 S1 10 11 (80,51) SLATCH1 R2 11 12 1 C3 12 98 10E-12 E2 13 98 (12,98) 1 R3 12 13 500 * * Power Supply Section
* Rev. D –9– Document Outline Features Applications General Description Pin Configurations Specifications Electrical Specifications Absolute Maximum Ratings Typical Performance Characteristics Applications Optimizing High Speed Performance Replacing the LT1016 Increasing Output Swing Output Loading Considerations Setup and Hold Times for Latching the Output Input Stage and Bias Currents Using Hysteresis SPICE Model Outline Dimensions Ordering Guide Revision History