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Datasheet AD96685, AD96687 (Analog Devices) - 5

ПроизводительAnalog Devices
ОписаниеUltrafast Comparators
Страниц / Страница8 / 5 — Typical Performance Characteristics–AD96685/AD96687. APPLICATIONS …
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Typical Performance Characteristics–AD96685/AD96687. APPLICATIONS INFORMATION

Typical Performance Characteristics–AD96685/AD96687 APPLICATIONS INFORMATION

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Typical Performance Characteristics–AD96685/AD96687 APPLICATIONS INFORMATION
Occasionally, one of the two comparator stages within the The AD96685/AD96687 comparators are very high speed devices. AD96687 will not be used. The inputs of the unused comparator Consequently, high speed design techniques must be employed should not be allowed to “float.” The high internal gain may to achieve the best performance. The most critical aspect of any cause the output to oscillate (possibly affecting the other com- AD96685/AD96687 design is the use of a low impedance parator which is being used) unless the output is forced into a ground plane. fixed state. This is easily accomplished by ensuring that the two inputs are at least one diode drop apart, while also grounding Another area of particular importance is power supply decoupling. the LATCH ENABLE input. Normally, both power supply connections should be separately decoupled to ground through 0.1 µF ceramic and 0.001 µF mica The best performance will be achieved with the use of proper capacitors. The basic design of comparator circuits makes the ECL terminations. The open-emitter outputs of the AD96685/ negative supply somewhat more sensitive to variations. As a AD96687 are designed to be terminated through 50 Ω resis- result, more attention should be placed on ensuring a “clean” tors to –2.0 V, or any other equivalent ECL termination. If high negative supply. speed ECL signals must be routed more than a few centimeters, MicroStrip or StripLine techniques may be required to ensure The LATCH ENABLE input is active LOW (latched). If the proper transition times and prevent output ringing. latching function is not used, the LATCH ENABLE input should be grounded (ground is an ECL logic HIGH). The LATCH The AD96685/AD96687 have been specifically designed to ENABLE input of the AD96687 should be tied to –2.0 V or left reduce propagation delay dispersion over an input overdrive “floating,” to disable the latching function. An alternate use of range of 100 mV to 1 V. Propagation delay dispersion is the the LATCH ENABLE input is as a hysteresis control input. By change in propagation delay which results from a change in varying the voltage at the LATCH ENABLE input for the the degree of overdrive (how far the switching point is exceeded AD96685 and the differential voltage between both latch by the input). The overall result is a higher degree of timing inputs for the AD96687, small variations in the hysteresis can accuracy since the AD96685/AD96687 are far less sensitive be achieved. to input variations than most comparator designs. REV. D –5–
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