Datasheet AD8253 (Analog Devices) - 10

AD8253 Data Sheet 20 12.0 120 10 10.5 I 100 B+ A) A) 0 9.0 n n ( ( T I G = 1000 B– N 80 NT –10 7.5 ) RE RRE B d G = 100 –20 6.0 CU 60 CUR T E RR ( AS S F CM G = 10 –30 4.5 BI F IOS O 40 UT P UT –40 3.0 IN INP 20 G = 1 –50 1.5 –60 0
8
0 –15 –10 –5 0 5 10 15
01
10
21
100 1k 10k 100k 1M
0 3- 3-
COMMON-MODE VOLTAGE (V)
98 98 06
FREQUENCY (Hz)
06 Figure 18. Input Bias Current and Offset Current vs. Common-Mode Voltage Figure 21. CMRR vs. Frequency, 1 kΩ Source Imbalance
30 15 25 10 20 AND A) (n 5 NT T 15 ) N /V V RRE µ 10 ( 0 CU URRE C IB– RR AS T E 5 CM BI S F IB+ –5 UT F O 0 INP IOS –10 –5 –10 –15 –60 –40 –20 0 20 40 60 80 100 120 140
190
–50 –30 –10 10 30 50 70 90 110 130
220 3- 3-
TEMPERATURE (°C)
98 98 06
TEMPERATURE (°C)
06 Figure 19. Input Bias Current and Offset Current vs. Temperature Figure 22. CMRR vs. Temperature, G = 1
120 80 G = 1000 70 100 G = 100 G = 1000 60 50 80 G = 100 ) B ) 40 d G = 1 B d 60 ( 30 RR ( G = 10 IN G = 10 CM GA 20 40 10 G = 1 0 20 –10 0 –20
23
10
20
100 1k 10k 100k 1M
0
1k 10k 100k 1M 10M 100M
-0 3- 83 98
FREQUENCY (Hz) FREQUENCY (Hz)
69 06 00 Figure 20. CMRR vs. Frequency Figure 23. Gain vs. Frequency Rev. B | Page 10 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ANALOG-TO-DIGITAL CONVERTER APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE