Datasheet AD8224 (Analog Devices) - 8

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AD8224 Data Sheet
VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = 25°C, G = 1, RL = 2 kΩ1, unless otherwise noted. Table 6 displays the specifications for the dynamic performance of each individual instrumentation amplifier.
Table 6. Dynamic Performance of Each Individual Amplifier—Single-Ended Output Configuration, VS = +5 V Test Conditions/ A Grade B Grade Parameter Comments Min Typ Max Min Typ Max Unit
DYNAMIC RESPONSE Small Signal Bandwidth −3 dB G = 1 1500 1500 kHz G = 10 800 800 kHz G = 100 120 120 kHz G =1000 14 14 kHz Settling Time 0.01% G = 1 ΔV = 3 V step 2.5 2.5 µs O G = 10 ΔV = 4 V step 2.5 2.5 µs O G = 100 ΔV = 4 V step 7.5 7.5 µs O G =1000 ΔV = 4 V step 60 60 µs O Settling Time 0.001% G = 1 ΔV = 3 V step 3.5 3.5 µs O G = 10 ΔV = 4 V step 3.5 3.5 µs O G = 100 ΔV = 4 V step 8.5 8.5 µs O G =1000 ΔV = 4 V step 75 75 µs O Slew Rate G = 1 to 100 2 2 V/µs 1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = 25°C, G = 1, RL = 2 kΩ1 unless otherwise noted. Table 7 displays the specifications for the dynamic performance of both amplifiers when used in the differential output configuration shown in Figure 64.
Table 7. Dynamic Performance of Both Amplifiers—Differential Output Configuration2, VS = +5 V A Grade B Grade Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit
DYNAMIC RESPONSE Small Signal Bandwidth −3 dB G = 1 1500 1500 kHz G = 10 800 800 kHz G = 100 120 120 kHz G =1000 14 14 kHz Settling Time 0.01% G = 1 ΔV = 3 V step 2.5 2.5 µs O G = 10 ΔV = 4 V step 2.5 2.5 µs O G = 100 ΔV = 4 V step 7.5 7.5 µs O G =1000 ΔV = 4 V step 60 60 µs O Settling Time 0.001% G = 1 ΔV = 3 V step 3.5 3.5 µs O G = 10 ΔV = 4 V step 3.5 3.5 µs O G = 100 ΔV = 4 V step 8.5 8.5 µs O G =1000 ΔV = 4 V step 75 75 µs O Slew Rate G = 1 to 100 2 2 V/µs 1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. 2 Refers to the differential configuration shown in Figure 64. Rev. D | Page 8 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Maximum Power Dissipation ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION REFERENCE TERMINAL LAYOUT Package Considerations Hidden Paddle Package Exposed Pad Package Common-Mode Rejection over Frequency Reference Power Supplies SOLDER WASH INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION RF INTERFERENCE COMMON-MODE INPUT VOLTAGE RANGE APPLICATIONS INFORMATION DRIVING AN ADC DIFFERENTIAL OUTPUT Setting the Common-Mode Voltage 2-Channel Differential Output Using a Dual Op Amp DRIVING A DIFFERENTIAL INPUT ADC First Antialiasing Filter Second Antialiasing Filter Reference DRIVING CABLING OUTLINE DIMENSIONS ORDERING GUIDE