150ksps, 10-Bit, 2-Channel Single-Ended, and1-Channel True-Differential ADCs in SOT23 and TDFNMAX1086–MAX1089 tCONV tACQ CNVST 1 4 8 12 SCLK DOUT B9 B0 HIGH-Z B8 B7 B6 B5 B4 B3 B2 B1 S1 S0 MSB LSB HIGH-Z SAMPLING INSTANT Figure 5a. Single Conversion AIN1 vs. GND (MAX1086/MAX1087), unipolar mode AIN+ vs. AIN- (MAX1088/MAX1089) tCONV tACQ CNVST 1 4 8 12 SCLK DOUT B9 B0 HIGH-Z B8 B7 B6 B5 B4 B3 B2 B1 S1 S0 MSB LSB HIGH-Z SAMPLING INSTANT Figure 5b. Single Conversion AIN2 vs. GND (MAX1086/MAX1087), bipolar mode AIN+ vs. AIN- (MAX1088/MAX1089) Analog Input ProtectionInternal Clock Internal protection diodes which clamp the analog input The MAX1086–MAX1089 operate from an internal oscilla- to VDD and GND allow the analog input pins to swing tor, which is accurate within 10% of the 4MHz specified from GND - 0.3V to VDD + 0.3V without damage. Both clock rate. This results in a worse case conversion time inputs must not exceed VDD by more than 50mV or be of 3.7µs. The internal clock releases the system micro- lower than GND by more than 50mV for accurate conver- processor from running the SAR conversion clock and sions. If an off-channel analog input voltage exceeds allows the conversion results to be read back at the the supplies, limit the input current to 2mA. processor’s convenience, at any clock rate from 0 to 8MHz. _______________________________________________________________________________________9
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