AOZ5312UQIPin DescriptionPin NumberPin NamePin Function 1 PWM PWM input signal from the controller IC. When DISB#=0V, the internal resistor divider will be disconnected and this pin will be at high impedance. 2 SMOD# Pull low to enable Discontinuous Mode of Operation (DCM), Diode Emulation or Skip Mode. There is an internal pull-down resistor to AGND. 3 VCC 5V Bias for Internal Logic Blocks. Ensure to position a 1µF MLCC directly between VCC and AGND (Pin 4). 4 AGND Signal Ground. 5 BOOT High-Side MOSFET Gate Driver supply rail. Connect a 100nF ceramic capacitor between BOOT and the PHASE (Pin 7). 6 NC Internally connected to VIN paddle. It can be left floating (no connect) or tied to VIN. 7 PHASE This pin is dedicated for bootstrap capacitor AC return path connection from BOOT (Pin 5). 8, 9, 10, 11 VIN Power stage High Voltage Input (Drain connection of High-Side MOSFET). 12, 13, 14, 15 PGND Power Ground pin for power stage (Source connection of Low-Side MOSFET). 16, 17, 18, 19, Switching node connected to the Source of High-Side MOSFET and the Drain of Low-Side 20, 21, 22, 23, VSWH MOSFET. These pins are used for Zero Cross Detection and Anti-Overlap Control as well as 24, 25, 26 main inductor terminal. 27 GL Low-Side MOSFET Gate connection. This is for test purposes only. 28 PGND Power Ground pin for High-Side and Low-Side MOSFET Gate Drivers. Ensure to connect 1µF directly between PGND and PVCC (Pin 29). 29 PVCC 5V Power Rail for High-Side and Low-Side MOSFET Drivers. Ensure to position a 1µF MLCC directly between PVCC and PGND (Pin 28). 30 THWN Thermal warning indicator. This is an open-drain output. When the temperature at the driver IC die reaches the Over Temperature Threshold, this pin is pulled low. 31 DISB# Output disable pin. When this pin is pulled to a logic low level, the IC is disabled. There is an internal pull-down resistor to AGND. Rev. 1.0 July 2019 www.aosmd.com Page 3 of 18
