Datasheet AOZ5312UQI (Alpha & Omega) - 8

AOZ5312UQI Logic Table and Timing Diagrams Table 1: Input Control Truth Table DISB# SMOD# PWM(1) GH (Not a Pin) GL
L X X L L H L H H L H L L L H, Forward IL L, Reverse IL H X Tri-State L L H H H H L H H L L H
Note:
1.Diode emulation mode is activated when SMOD# is LOW and PWM transition from HIGH to Tri-State. Zero Cross Detection (ZCD) at IL*Rdson(LS) = 0.5mV to turn off GL. VPWMH PWM VPWML tPDLL tPDHL GL 1V 1V tPDLU 90% VSWH tPDHU 1V 1V
Figure 1. PWM Logic Input Timing Diagram
Rev. 1.0 July 2019
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