Datasheet ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 (Analog Devices)

ПроизводительAnalog Devices
ОписаниеSHARC Processor
Страниц / Страница71 / 1 — SHARC Processor. ADSP-21483/. ADSP-21486/. ADSP-21487. /ADSP-21488. …
ВерсияH
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Язык документаанглийский

SHARC Processor. ADSP-21483/. ADSP-21486/. ADSP-21487. /ADSP-21488. /ADSP-21489. FEATURES

Datasheet ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 Analog Devices, Версия: H

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SHARC Processor ADSP-21483/ ADSP-21486/ ADSP-21487 /ADSP-21488 /ADSP-21489 FEATURES High performance 32-bit/40-bit floating-point processor The ADSP-2148x processors are available with unique audio- optimized for high performance audio processing centric peripherals, such as the digital applications Single-instruction, multiple-data (SIMD) computational interface, serial ports, precision clock generators, S/PDIF architecture transceiver, asynchronous sample rate converters, input On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip data port, and more ROM For complete ordering information, see Ordering Guide on Up to 450 MHz operating frequency Page 70 Code compatible with all other members of the SHARC family AEC-Q100 qualified for automotive applications Internal Memory SIMD Core Block 0 Block 1 Block 2 Block 3 RAM/ROM RAM/ROM RAM RAM Instruction 5 Stage Cache Sequencer
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B0D B1D B2D B3D Core 64-BIT 64-BIT 64-BIT 64-BIT DAG1/2 Timer DMD DMD 64-BIT 64-BIT PEx PEy Core Bus Internal Memory I/F Cross Bar PMD PMD 64-BIT 64-BIT FLAGx/IRQx/ THERMAL IOD0 32-BIT EPD BUS 64-BIT JTAG TMREXP DIODE PERIPHERAL BUS 32-BIT IOD1 32-BIT IOD0 BUS FFT DTCP/ FIR MTM IIR PERIPHERAL BUS EP SPEP BUS CORE PCG TIMER S/PDIF PCG ASRC PDAP/ SPORT CORE PWM SDRAM FLAGS/ TWI SPI/B UART IDP WDT AMI C-D 1-0 Tx/Rx A-D 3-0 7-0 FLAGS 3-0 CTL PWM3-1 7-0 DPI Routing/Pins DAI Routing/Pins External Port Pin MUX External DPI Peripherals DAI Peripherals Peripherals Port
Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies. Technical Support www.analog.com
Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
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