link to page 1 link to page 1 link to page 5 link to page 5 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 The diagram on Page 1 shows the two clock domains that make SIMD Computational Engine up the ADSP-2148x processors. The core clock domain contains The ADSP-2148x contains two computational processing ele- the following features: ments that operate as a single-instruction, multiple-data • Two processing elements (PEx, PEy), each of which com- (SIMD) engine. The processing elements are referred to as PEX prises an ALU, multiplier, shifter, and data register file and PEY and each contains an ALU, multiplier, shifter, and reg- • Data address generators (DAG1, DAG2) ister file. PEx is always active, and PEy may be enabled by setting the PEYEN mode bit in the MODE1 register. SIMD • Program sequencer with instruction cache mode allows the processor to execute the same instruction in • PM and DM buses capable of supporting 2x64-bit data both processing elements, but each processing element operates transfers between memory and the core at every core pro- on different data. This architecture is efficient at executing math cessor cycle intensive DSP algorithms. • One periodic interval timer with pinout SIMD mode also affects the way data is transferred between • On-chip SRAM (5 Mbit) and mask-programmable ROM memory and the processing elements because twice the data (4 Mbit) bandwidth is required to sustain computational operation in the processing elements. Therefore, entering SIMD mode also dou- • JTAG test access port for emulation and boundary scan. bles the bandwidth between memory and the processing The JTAG provides software debug through user break- elements. When using the DAGs to transfer data in SIMD points which allows flexible exception handling. mode, two data values are transferred with each memory or reg- The block diagram of the ADSP-2148x on Page 1 also shows the ister file access. peripheral clock domain (also known as the I/O processor) Independent, Parallel Computation Units which contains the following features: • IOD0 (periphera l DMA) and IOD1 (external port DMA) Within each processing element is a set of computational units. buses for 32-bit data transfers The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all opera- • Peripheral and external port buses for core connection tions in a single cycle and are arranged in parallel, maximizing • External port with an AMI and SDRAM controller computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, • 4 units for PWM control the parallel ALU and multiplier operations occur in both pro- • 1 memory-to-memory (MTM) unit for internal-to-internal cessing elements. These computation units support IEEE 32-bit memory transfers single-precision floating-point, 40-bit extended precision float- • Digital applications interface that includes four precision ing-point, and 32-bit fixed-point data formats. clock generators (PCG), an input data port (IDP/PDAP) Timer for serial and parallel interconnects, an S/PDIF receiver/transmitter, four asynchronous sample rate con- The processor contains a core timer that can generate periodic verters, eight serial ports, and a flexible signal routing unit software interrupts. The core timer can be configured to use (DAI SRU). FLAG3 as a timer expired signal. • Digital peripheral interface that includes two timers, a Data Register File 2-wire interface (TWI), one UART, two serial peripheral interfaces (SPI), 2 precision clock generators (PCG), pulse Each processing element contains a general-purpose data regis- width modulation (PWM), and a flexible signal routing ter file. The register files transfer data between the computation unit (DPI SRU2). units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, As shown in the SHARC core block diagram on Page 5, the combined with the processor’s enhanced Harvard architecture, processor uses two computational units to deliver a significant allow unconstrained data flow between computation units and performance increase over the previous SHARC processors on a internal memory. The registers in PEX are referred to as range of DSP algorithms. With its SIMD computational hard- R0–R15 and in PEY as S0–S15. ware, the processors can perform 2.7 GFLOPS running at 450 MHz. Context SwitchFAMILY CORE ARCHITECTURE Many of the processor’s registers have secondary registers that can be activated during interrupt servicing for a fast context The ADSP-2148x is code compatible at the assembly level with switch. The data registers in the register file, the DAG registers, the ADSP-2147x, ADSP-2146x, ADSP-2137x, ADSP-2136x, and the multiplier result registers all have secondary registers. ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first The primary registers are active at reset, while the secondary generation ADSP-2106x SHARC processors. The ADSP-2148x registers are activated by control bits in a mode control register. shares architectural features with the ADSP-2126x, ADSP- 2136x, ADSP-2137x, ADSP-2146x and ADSP-2116x SIMD SHARC processors, as shown in Figure 2 and detailed in the fol- lowing sections. Rev. H | Page 4 of 71 | February 2020 Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
