link to page 6 link to page 7 link to page 6 link to page 7 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 subtract in both processing elements while branching and fetch- SDRAM memory. This support is not extended to the ing up to four 32-bit values from memory, all in a single asynchronous memory interface (AMI). Source modules need instruction. to be built using the VISA option, in order to allow code genera- tion tools to create these more efficient opcodes. Variable Instruction Set Architecture (VISA)On-Chip Memory In addition to supporting the standard 48-bit instructions from previous SHARC processors, the ADSP-2148x supports new The ADSP-21483 and the ADSP-21488 processors contain instructions of 16 and 32 bits. This feature, called Variable 3 Mbits of internal RAM (Table 3) and the ADSP-21486, Instruction Set Architecture (VISA), drops redundant/unused ADSP-21487, and ADSP-21489 processors contain 5 Mbits of bits within the 48-bit instruction to create more efficient and internal RAM (Table 4). Each memory block supports single- compact code. The program sequencer supports fetching these cycle, independent accesses by the core processor and I/O 16-bit and 32-bit instructions from both internal and external processor. Table 3. Internal Memory Space (3 MBits—ADSP-21483/ADSP-21488)1IOP Registers 0x0000 0000–0x0003 FFFFExtended Precision Normal orLong Word (64 Bits)Instruction Word (48 Bits)Normal Word (32 Bits)Short Word (16 Bits) Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF 0x0008 0000–0x0008 AAA9 0x0008 0000–0x0008 FFFF 0x0010 0000–0x0011 FFFF Reserved Reserved Reserved Reserved 0x0004 8000–0x0004 8FFF 0x0008 AAAA–0x0008 BFFF 0x0009 0000–0x0009 1FFF 0x0012 0000–0x0012 3FFF Block 0 SRAM Block 0 SRAM Block 0 SRAM Block 0 SRAM 0x0004 9000–0x0004 CFFF 0x0008 C000–0x0009 1554 0x0009 2000–0x0009 9FFF 0x0012 4000–0x0013 3FFF Reserved Reserved Reserved Reserved 0x0004 D000–0x0004 FFFF 0x0009 1555–0x0009 FFFF 0x0009 A000–0x0009 FFFF 0x0013 4000–0x0013 FFFF Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF 0x000A 0000–0x000A AAA9 0x000A 0000–0x000A FFFF 0x0014 0000–0x0015 FFFF Reserved Reserved Reserved Reserved 0x0005 8000–0x0005 8FFF 0x000A AAAA–0x000A BFFF 0x000B 0000–0x000B 1FFF 0x0016 0000–0x0016 3FFF Block 1 SRAM Block 1 SRAM Block 1 SRAM Block 1 SRAM 0x0005 9000–0x0005 CFFF 0x000A C000–0x000B 1554 0x000B 2000–0x000B 9FFF 0x0016 4000–0x0017 3FFF Reserved Reserved Reserved Reserved 0x0005 D000–0x0005 FFFF 0x000B 1555–0x000B FFFF 0x000B A000–0x000B FFFF 0x0017 4000–0x0017 FFFF Block 2 SRAM Block 2 SRAM Block 2 SRAM Block 2 SRAM 0x0006 0000–0x0006 1FFF 0x000C 0000–0x000C 2AA9 0x000C 0000–0x000C 3FFF 0x0018 0000–0x0018 7FFF Reserved Reserved Reserved Reserved 0x0006 2000– 0x0006 FFFF 0x000C 2AAA–0x000D FFFF 0x000C 4000–0x000D FFFF 0x0018 8000–0x001B FFFF Block 3 SRAM Block 3 SRAM Block 3 SRAM Block 3 SRAM 0x0007 0000–0x0007 1FFF 0x000E 0000–0x000E 2AA9 0x000E 0000–0x000E 3FFF 0x001C 0000–0x001C 7FFF Reserved Reserved Reserved Reserved 0x0007 2000–0x0007 FFFF 0x000E 2AAA–0x000F FFFF 0x000E 4000–0x000F FFFF 0x001C 8000–0x001F FFFF 1 Some ADSP-2148x processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Contact your Analog Devices sales representative for additional details. The processor’s SRAM can be configured as a maximum of most efficient when one block stores data using the DM bus for 160k words of 32-bit data, 320k words of 16-bit data, 106.7k transfers, and the other block stores instructions and data using words of 48-bit instructions (or 40-bit data), or combinations of the PM bus for transfers. different word sizes up to 5 megabits. All of the memory can be Using the DM bus and PM buses, with one bus dedicated to a accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit memory block, assures single-cycle execution with two data floating-point storage format is supported that effectively dou- transfers. In this case, the instruction must be available in the bles the amount of data that may be stored on-chip. Conversion cache. between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each mem- The memory maps in Table 3 and Table 4 display the internal ory block can store combinations of code and data, accesses are memory address space of the processors. The 48-bit space sec- tion describes what this address range looks like to an Rev. H | Page 6 of 71 | February 2020 Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
