Datasheet K6R1016V1D (Samsung) - 7

for AT&T K6R1016V1D CMOS SRAM TIMING WAVEFORM OF READ CYCLE(2)
(WE=VIH) tRC
Address
tAA tHZ(3,4,5) tCO
CS
tBA tBHZ(3,4,5)
UB, LB
tBLZ(4,5) tOHZ tOE
OE
tOLZ tDH tLZ(4,5)
Data out
High-Z Valid Data tPU tPD
V I CC CC
50% 50%
Current ISB NOTES
(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1)
(OE =Clock) tWC
Address
tAW tWR(5)
OE
tCW(3)
CS
tBW
UB, LB
tAS(4) tWP(2)
WE
tDW tDH
Data in
High-Z Valid Data High-Z tOHZ(6)
Data out Revision 3.0
- 7 -
June 2002