A product Line of Diodes Incorporated PS508/PS509Pin Configuration PS509 A0 1 16 A1 EN 2 15 GND VSS 3 14 VDD S1A 4 13 S1B S2A 5 12 S2B S3A 6 11 S3B S4A 7 10 S4B DA 8 9 DB Pin DescriptionPin#Pin NameTypeDescription 1 A0 I Address line 0. 16 A1 I Address line 1. 8 DA I/O Drain pin A. Can be an input or output. 9 DB I/O Drain pin B. Can be an input or output. 2 EN I Active high digital input. When this pin is low, all switches are turned off. When this pin is high, the A[1:0] logic inputs determine which pair of switches is turned on. 15 GND Pwr Ground (0 V) reference 4 S1A I/O Source pin 1A. Can be an input or output. 5 S2A I/O Source pin 2A. Can be an input or output. 6 S3A I/O Source pin 3A. Can be an input or output. 7 S4A I/O Source pin 4A. Can be an input or output. 13 S1B I/O Source pin 1B. Can be an input or output. 12 S2B I/O Source pin 2B. Can be an input or output. 11 S3B I/O Source pin 3B. Can be an input or output. 10 S4B I/O Source pin 4B. Can be an input or output. 14 VDD Pwr Positive power supply. This pin is the most positive power supply potential. For reliable opera- tion, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. Negative power supply. This pin is the most negative power supply potential. In single supply 3 VSS Pwr applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. Note: I = Input, O = Output and I/O = Input/Output PS508/PS509 Document Number DS41784 Rev 2-2 3 www.diodes.com June 2020 Diodes Incorporated
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