link to page 10 link to page 11 MLX75026 QVGA Time-of-Flight Sensor PRELIMINARY DATASHEET 3.4.
Power Consumption The total power consumption is split over four domains, none of the four domains are consuming at the same time. VDDMIX and VDDIF are dominantly active during the integration time, VDD D and VDDA during the readout time and a small amount of VDDD is active constantly. As shown below in Figure 4. Figure 4: Power domains The following table lists the absolute peak current per domain, however the typical duty cycle of each active period is only around 10%. ParameterSymbol Typ.Max. 1 Unit Analog Supply Current IDDA 26.6 27.4 mA MIX Drivers Supply Current IDDMIX 544.1 1350.52 mA Digital Supply Current IDDD 91.7 120.0 mA I/O Supply Current IDDIF 2.1 2.6 mA Table 8: Peak current Note1 : Max. is the worst case peak current over the full ambient operating temperature range, over the full process variation and at worst case settings. Note2 : This value is the worst case peak current at -40˚C ambient temperature but realistically the system will not operate at this temperature so for PSU dimensioning we suggest to take into account the typical value. See Figure 6 for more information. Taking the according duty cycles into account will lead to the following average power consumption per domain. Application AApplication BParameterSymbol Typ.1 Max.2 Typ.1 Max.2 Unit Analog Supply PDDA 14.8 15.2 19.0 19.6 mW MIX Drivers PDDMIX 24.8 52.7 114.0 241.9 mW Supply Digital Supply PDDD 48.3 62.3 50.2 64.7 mW I/O Supply PDDIF 1.6 2.0 2.1 2.6 mW Total Supply P 88.5 141.3 185.3 355.3 mW Table 9: Power consumption Note1 : Typical values are the average power consumption with nominal voltage levels (at room temperature) for two defined application conditions: Preliminary Datasheet v0.5 Page 10 of 64 Document Outline Table of Contents Document Revision History Ordering Information 1. System Architecture 2. Sensor Block Diagram 3. Electrical Specifications 3.1. Absolute Maximum Ratings 3.2. Typical Operating Conditions 3.3. Video Interface 3.3.1. MIPI DC specification 3.3.2. MIPI AC specification 3.4. Power Consumption 3.5. Maximum Distance Frame Rate 3.6. Decoupling Recommendations 3.7. Power-up Sequence 3.8. Input Clock Requirements 3.9. I2C Specifications 4. Optical Characteristics 4.1. QVGA Pixel Array Configuration 4.2. Pixel & Image Array Characteristics 4.3. CRA (Chief Ray Angle) 4.4. MTF (Modulation Transfer Function) 4.5. Application Lens Design Recommendations 5. Communication Interface(s) 5.1. I2C (Inter-Integrated Circuit) 5.1.1. I2C Timing Sequence 5.1.2. Single I2C Read 5.1.3. Sequential I2C Read 5.1.4. Single I2C Write 5.1.5. Sequential I2C Write 5.1.6. I2C Slave Address 5.2. MIPI Alliance CSI-2 Description 5.2.1. Packet Structure 5.2.2. Data Format RAW12 5.2.2.1. Data Format in 4 Lane MIPI Configuration 5.2.2.2. Data Format in 2 Lane MIPI Configuration 6. Start-up Sequence 6.1. Initialization Process 6.2. Initialization Register Map 7. Register Settings 7.1. Video Output Configuration 7.2. Modes of Operation 7.3. Data Output Modes 7.4. HMAX & Frame Read-Out Time 7.4.1. PLLSSETUP 7.4.2. PRETIME 7.4.3. RANDNM0 7.5. PARAM_HOLD 7.6. USER_ID Register 7.7. Modulation Frequency 7.8. Frame Structure & Frame Rate 7.9. FRAME_STARTUP 7.10. FRAME_TIME 7.11. PHASE_COUNT 7.12. Px_PREHEAT, Px_PREMIX 7.13. Px_INTEGRATION 7.14. Px_PHASE_SHIFT 7.15. Px_PHASE_IDLE (or V-blanking) 7.16. Px_LEDEN 7.17. Px_DMIX0, Px_DMIX1 & Px_STATIC_LED 7.18. Analog Delay Setting 7.18.1. Coarse Delay 7.18.2. Fine Delay 7.18.3. Super Fine 7.19. Pixel Binning 7.20. Region of Interest (ROI) 7.21. Flip & Mirror 7.22. Temperature Sensor 7.23. Pixel & Phase Statistics 7.24. PN9 Test Pattern 7.25. Duty Cycle Adjustment 7.26. Illumination Signal (subLVDS or CMOS) 8. MetaData Description 8.1. Embedded Data Format in 4 Lane MIPI Configuration 8.2. Embedded Data Format in 2 Lane MIPI Configuration 9. Distance & Amplitude Calculation 10. Package Outline 10.1. Pinout & Equivalent I/O Circuitry 10.2. Mechanical Dimensions 10.3. PCB Landing Pattern & Layout Recommendations 10.4. Package Marking 10.5. Cover Tape Removal Disclaimer
