Datasheet AD8045 (Analog Devices) - 5

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Data Sheet AD8045 ABSOLUTE MAXIMUM RATINGS Table 3.
PD = Quiescent Power + (Total Drive Power – Load Power)
Parameter Rating
  P = (V × I ) 2 V V V S OUT OUT + × Supply Voltage 12.6 V – D S S   2 R  R L L Power Dissipation See Figure 4 Common-Mode Input Voltage −V RMS output voltages should be considered. If R S − 0.7 V to +VS + 0.7 V L is referenced Differential Input Voltage ±V to −VS, as in single-supply operation, the total drive power is S Exposed Paddle Voltage −V VS × IOUT. If the rms signal levels are indeterminate, consider S Storage Temperature Range −65°C to +125°C the worst case, when VOUT = VS/4 for RL to midsupply. Operating Temperature Range −40°C to +125°C 2 4 P = (V × I ) (V / ) S + Lead Temperature (Soldering 10 sec) 300°C D S S RL Junction Temperature 150°C In single-supply operation with RL referenced to −VS, worst case Stresses at or above those listed under Absolute Maximum is VOUT = VS/2. Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these Airflow increases heat dissipation, effectively reducing θJA. Also, or any other conditions above those indicated in the operational more metal directly in contact with the package leads and exposed section of this specification is not implied. Operation beyond paddle from metal traces, through holes, ground, and power the maximum operating conditions for extended periods may planes reduces θJA. affect product reliability. Figure 4 shows the maximum safe power dissipation in the
THERMAL RESISTANCE
package vs. the ambient temperature for the exposed paddle SOIC (80°C/W) and LFCSP (93°C/W) package on a JEDEC θJA is specified for the worst-case conditions; that is, θJA is specified standard 4-layer board. θJA values are approximations. for the device soldered in the circuit board for surface-mount
4.0
packages.
3.5 Table 4. Thermal Resistance 3.0 Package Type θJA θJC Unit
SOIC 80 30 °C/W
2.5
LFCSP 93 35 °C/W
2.0 Maximum Power Dissipation 1.5 SOIC
The maximum safe power dissipation for the AD8045 is limited by the associated rise in junction temperature (T
1.0
J) on the die. At
LFCSP
approximately 150°C, which is the glass transition temperature,
0.5 MAXIMUM POWER DISSIPATION (Watts)
the properties of the plastic change. Even temporarily exceeding
0.0
this temperature limit may change the stresses that the package
–40 –20 0 20 40 60 80 100 120
exerts on the die, permanently shifting the parametric performance
AMBIENT TEMPERATURE (°C)
04814-0-080 Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board of the AD8045. Exceeding a junction temperature of 175°C for an extended period of time can result in changes in silicon devices,
ESD CAUTION
potentially causing degradation or loss of functionality. The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the AD8045 drive at the output. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Rev. C | Page 5 of 24 Document Outline Features Applications Connection Diagrams General Description Table of Contents Revision History Specifications with ±5 V Supply Specifications with +5 V Supply Absolute Maximum Ratings Thermal Resistance Maximum Power Dissipation ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Circuit Configurations Wideband Operation Theory of Operation Frequency Response DC Errors Output Noise Applications Information Low Distortion Pinout High Speed ADC Driver 90 MHz Active Low-Pass Filter (LPF) Printed Circuit Board Layout Signal Routing Power Supply Bypassing Grounding Exposed Paddle Driving Capacitive Loads Outline Dimensions Ordering Guide