Datasheet AD8016 (Analog Devices) - 5

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Data Sheet AD8016 ABSOLUTE MAXIMUM RATINGS
The output stage of the AD8016 is designed for maximum load
Table 4.
current capability. As a result, shorting the output to common
Parameter Rating
can cause the AD8016 to source or sink 2000 mA. To ensure Supply Voltage 26.4 V proper operation, it is necessary to observe the maximum Internal Power Dissipation power derating curves. Direct connection of the output to SOIC_W_BAT Package1 1.4 W either power supply rail can destroy the device. TSSOP_EP Package2 1.4 W Input Voltage (Common-Mode) ±V
8
S Differential Input Voltage ±VS
7 )
Output Short-Circuit Duration Observe power derating
W (
curves
ON 6
Storage Temperature Range −65°C to +125°C
TI A
Operating Temperature Range −40°C to +85°C
IP S 5 IS
Lead Temperature Range (Soldering 10 sec) 300°C
D 4 R E SOIC_W_BAT
1 Specification is for device on a 4-layer board with 10 inches2 of 1 oz copper
W O
at 85°C 24-lead SOIC_W_BAT package: θ
3
JA = 28°C/W.
P M TSSOP-EP
2 Specification is for device on a 4-layer board with 9 inches2 of 1 oz copper at 85°C 28-lead (TSSOP_EP) package: θ
MU 2
JA = 29°C/W.
XI
Stresses above those listed under Absolute Maximum Ratings
MA 1
may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any
0 0 10 20 30 40 50 60 70 80 90
005 other conditions above those indicated in the operational
AMBIENT TEMPERATURE (°C)
01019- section of this specification is not implied. Exposure to absolute Figure 3. Maximum Power Dissipation vs. Temperature for AD8016 for maximum rating conditions for extended periods may affect TJ = 125 °C device reliability.
ESD CAUTION MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8016 is limited by the associated rise in junction temper- ature. The maximum safe junction temperature for a plastic encapsulated device is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric perfor- mance due to a change in the stresses exerted on the die by the package. Rev. C | Page 5 of 20 Document Outline Features Pin Configurations General Description Revision History Specifications Logic Inputs (CMOS Compatible Logic) Absolute Maximum Ratings Maximum Power Dissipation ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuts Theory of Operation Power Supply and Decoupling Feedback Resistor Selection Bias Pin and PWDN Features Thermal Shutdown Applications Information Multitone Power Ratio (MTPR) Generating DMT Power Dissipation Thermal Enhancements and PCB Layout Thermal Testing Air Flow Test Conditions DUT Power Thermal Resistance PCB Dimensions of a Differential Driver Circuit Experimental Results Outline Dimensions Ordering Guide