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Datasheet OP27 (Analog Devices)

ПроизводительAnalog Devices
ОписаниеLow Noise, Precision Operational Amplifier
Страниц / Страница21 / 1 — FEATURES. PIN CONFIGURATIONS. Low noise: 80 nV p-p (0.1 Hz to 10 Hz), 3 …
ВерсияH
Формат / Размер файлаPDF / 416 Кб
Язык документаанглийский

FEATURES. PIN CONFIGURATIONS. Low noise: 80 nV p-p (0.1 Hz to 10 Hz), 3 nV/√Hz. BAL. Low drift: 0.2 µV/°C. BAL 1

Datasheet OP27 Analog Devices, Версия: H

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Low Noise, Precision Operational Amplifier Data Sheet OP27
FEATURES PIN CONFIGURATIONS Low noise: 80 nV p-p (0.1 Hz to 10 Hz), 3 nV/√Hz BAL Low drift: 0.2 µV/°C BAL 1 V+ High speed: 2.8 V/µs slew rate, 8 MHz gain bandwidth OP27 Low VOS: 10 µV –IN 2 OUT CMRR: 126 dB at VCM of ±11 V +IN 3 NC High open-loop gain: 1.8 million
1 0
Available in die form 4V– (CASE)
-0 7 1
NC = NO CONNECT
3 0 0
GENERAL DESCRIPTION
Figure 1. 8-Lead TO-99 (J-Suffix) The OP27 precision operational amplifier combines the low offset and drift of the OP07 with both high speed and low noise.
1 8 VOS TRIM VOS TRIM OP27
Offsets down to 25 µV and maximum drift of 0.6 µV/°C make
–IN 2 7 V+
the OP27 ideal for precision instrumentation applications. Low
+IN 3 6 OUT
noise, en = 3.5 nV/√Hz, at 10 Hz, a low 1/f noise corner
V– 4 5 NC
2 0 -0 frequency of 2.7 Hz, and high gain (1.8 million), allow accurate 7 1
NC = NO CONNECT
3 0 0 high-gain amplification of low-level signals. A gain bandwidth product of 8 MHz and a 2.8 V/µs slew rate provide excellent Figure 2. 8-Lead CERDIP – Glass Hermetic Seal (Z-Suffix), 8-Lead PDIP (P-Suffix), and 8-Lead SOIC (S-Suffix) dynamic accuracy in high speed, data-acquisition systems. A low input bias current of ±10 nA is achieved by use of a bias current cancellation circuit. Over the military temperature range, this circuit typical y holds IB and IOS to ±20 nA and 15 nA, respectively. The output stage has good load driving capability. A guaranteed swing of ±10 V into 600 Ω and low output distortion make the OP27 an excellent choice for professional audio applications. (Continued on Page 3)
FUNCTIONAL BLOCK DIAGRAM V+ R3 R4 C2 1 8 Q6 Q22 Q46 V C1 R11 OS ADJ. R21 R23 R24 Q21 Q23 Q24 R9 Q20 Q19 Q1A Q1B Q2B Q2A R12 OUTPUT NONINVERTING C3 C4 INPUT (+) R5 Q3 INVERTING Q26 Q11 Q12 Q45 INPUT (–) Q27 Q28 1 R1 AND R2 ARE PERMANENTLY ADJUSTED AT WAFER TEST FOR MINIMUM OFFSET VOLTAGE
3 0 -0 7 1
V–
3 0 0 Figure 3.
Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©1981–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
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