Datasheet LT8550 (Analog Devices) - 4

LT8550
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, REG = 5V, VCC = 5V, SHDN = High, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS
(ISPn-ISNn) Voltage In Regulation IAMPP = 2.20V, IAMPN = 0V, ILIM = 0V, ISNn = 12V l 21.25 26.75 mV IAMPP = 0.60V, IAMPN = 0V, ILIM = 0V, ISNn = 12V l –26.75 –21.25 mV IAMPP = 2.20V, IAMPN = 0V, ILIM = REG, ISNn = 12V l 45.0 51.0 mV IAMPP = 0.60V, IAMPN = 0V, ILIM = REG, ISNn = 12V l –51.0 –45.0 mV IAMPP = 2.20V, IAMPN = 0V, ILIM = Float, ISNn = 12V l 67.25 76.75 mV IAMPP = 0.60V, IAMPN = 0V, ILIM = Float, ISNn = 12V l –76.75 –67.25 mV (ISP-ISN) to IAMPP Voltage Gain ILIM = 0V, Master LT8550, ISN = 0V 33.3 ILIM = REG, Master LT8550, ISN = 0V 16.7 ILIM = FLOAT, Master LT8550, ISN = 0V 11.1 IAMPP Sourcing Current Limit (ISP-ISN) = 0mV, Master LT8550 l 250 µA IAMPP Sinking Current Limit (ISP-ISN) = 0mV, Master LT8550 l 60 µA IAMPP Load Regulation ILOAD = –200µA to 50µA, Master LT8550 1 mV IAMPP Pin Bias Current IAMPP = 1.2V, Slave LT8550 3 µA IAMPP = 2.4V, Slave LT8550 6 µA Mismatch Between (ISPn-ISNn) and Master ILIM = REG l –6 6 % LT8550’s (ISP-ISN) in Regulation –4.75 4.75 % Mismatch Between (ISPn-ISNn) and Master ILIM = FLOAT l –6 6 % LT8550’s (ISP-ISN) in Regulation –5.5 5.5 % Mismatch Between (ISPn-ISNn) and Master ILIM = 0V l –10 10 % LT8550’s (ISP-ISN) in Regulation –8 8 %
Oscillator
CLK1 Frequency RT/MS = 24.3kΩ, Master LT8550 l 900 1000 1100 kHz RT/MS = 100 kΩ, Master LT8550 l 236 250 264 kHz RT/MS = 249kΩ, Master LT8550 l 90 100 110 kHz Switching Frequency Range Free-Running l 100 1000 kHz Synchronizing l 125 1000 kHz SYNC High Level for Synchronization l 1.2 V SYNC Low Level for Synchronization l 0.8 V CLK1, CLK2 Rise Time CLOAD = 220pF, Master LT8550 (Note 4) 7 ns CLK1, CLK2 Fall Time CLOAD = 220pF, Master LT8550 (Note 4) 5 ns CLK2 Rising Threshold Slave LT8550 l 4.0 V CLK2 Falling Threshold Slave LT8550 l 1.0 V PHS1, PHS2 High Rising Threshold l 4.65 V PHS1, PHS2 High Threshold Hysteresis 80 mV PHS1, PHS2 Low Falling Threshold l 0.3 V PHS1, PHS2 Low Threshold Hysteresis 80 mV PHS1, PHS2 Impedance at Floating 11 kΩ PHS3 Rising Threshold l 4.65 V PHS3 Threshold Hysteresis 80 mV
REG LDO
REG Voltage REGSNS = 5V, IAMPN = 0V, ILOAD = 45mA l 4.9 5.1 5.3 V REG LDO Current Limit VIN = 12V, REGSNS = 5V, REG, VCC = 4V 250 mA VIN = 24V, REGSNS = 5V, REG, VCC = 4V 145 mA REG LDO Gate Drive Clamp Voltage (VIN – REGDRV) Voltage, REG, VCC = 4.5V 5.3 V REG Load Regulation ILOAD = 0 to 100mA, REGSNS = 5V, IAMPN = 0V 90 mV REGSNS Pin Bias Current REGSNS = 5V 12 µA Rev. 0 4 For more information www.analog.com