LTC3894 FUNCTIONAL DIAGRAM ROVLO1 ROVLO2 VIN CIN 8V 0.8V OVLO UVLO VIN + CAP – + 20µA REXTG – + – CAP DRVUV/EXTG + DRUV C EXT EXTG 1.26V – NMOS SHDN GATE EXTS DRIVER LDO CEXTS OPTIONAL GATE LOGIC GATE CONTROL MP DRIVER RUN Q L VIN + S R VOUT Burst Mode IN 1.26V – C OPERATION OUT LDO CCAP CLOCK + PLLIN/MODE O.425V OUT MODE/CLOCK DETECT – V CAP IN – 8V D1 PLL SYSTEM – ICMP + SENSE+ 20µA VCO + FREQ – SENSE– R + FREQ 10µA TRACK/SS GND + VOUT + 0.8V SLOPE SHDN CSS COMPENSATION – RPGD EA OV + O.88V R PGOOD (g FB2 m = 2mS) VFB – DELAY 100µs RFB1 UV + – O.72V ITH PGUV 3894 FD RPGUV2 RITH R C PGUV1 ITH1 Rev. A 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
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