Datasheet ADP1853 (Analog Devices) - 7

Data Sheet ADP1853 SIMPLIFIED BLOCK DIAGRAM VIN VCCO OV THERMAL LDO REF 0.6V SHUTDOWN UV AGND UVLO SL_TH 0.6V SLAVE FB LOGIC EN_SW VCCO EN OV LOGIC CLKOUT UV SYNC 12.5kΩ 1MΩ OV_TH PGOOD OSCILLATOR FREQ SLAVE FB COMP VCCO UV_TH FB – ERROR + AMPLIFIER TRK CLK SS + BST + EN_SW DH VREF = 0.6V OVER_LIM DRIVER LOGIC OV VCCO – CONTROL AND SW PULSE SKIP STATE 6.5µA 0.9V MACHINE CS + VCCO LOGIC OV FAULT – DL 3kΩ EN OVER_LIM + PWM COMPARATOR CS GAIN DCM + SLOPE COMPENSATION PGND ZERO – RAMP AND RAMP GENERATOR CROSS DETECT AV = 0,* 3, 6, 12 – CURRENT SENSE AMPLIFIER + VCCO + CURRENT-LIMIT 50µA OVER_LIM CONTROL – ILIM
002
*0 (ZERO) GAIN IS FOR VOLTAGE MODE WITH RAMP FROM 0.7V TO 2.2V.
10594- Figure 2. Rev. A | Page 7 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION SIMPLIFIED BLOCK DIAGRAM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CONTROL ARCHITECTURE OSCILLATOR FREQUENCY SYNCHRONIZATION PWM OR PULSE SKIP MODE OF OPERATION CLKOUT SIGNAL SYNCHRONOUS RECTIFIER AND DEAD TIME INPUT UNDERVOLTAGE LOCKOUT INTERNAL LINEAR REGULATOR OVERVOLAGE PROTECTION POWER GOOD SHORT-CIRCUIT AND CURRENT-LIMIT PROTECTION ENABLE/DISABLE CONTROL THERMAL OVERLOAD PROTECTION INTERLEAVED DUAL-PHASE OPERATION APPLICATIONS INFORMATION ADISIMPOWER DESIGN TOOL SETTING THE OUTPUT VOLTAGE SOFT START SETTING THE CURRENT LIMIT ACCURATE CURRENT-LIMIT SENSING INPUT CAPACITOR SELECTION VIN PIN FILTER BOOST CAPACITOR SELECTION INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION MOSFET SELECTION LOOP COMPENSATION—VOLTAGE MODE Type III Compensation LOOP COMPENSATION—CURRENT MODE Setting the Slope Compensation Setting the Current Sense Gain Type II Compensation SWITCHING NOISE AND OVERSHOOT REDUCTION VOLTAGE TRACKING Coincident Tracking Ratiometric Tracking PCB LAYOUT GUIDLINES TYPICAL OPERATING CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE