STD30PF03LT4STD30PF03L-1 P-channel 30 V - 0.025 Ω - 24 A - DPAK / IPAK STripFET™ II Power MOSFET FeaturesTypeVDSSRDS(on) maxID STD30PF03LT4 30 V < 0.028 Ω 24 A STD30PF03L-1 30 V < 0.028 Ω 24 A 3 3 2 1 1 ■ Standard outline for easy automated surface DPAK mount assembly IPAK ■ Low threshold device ■ Low gate charge Application ■ Switching applications Figure 1.Internal schematic diagramDescription This Power MOSFET is the latest development of STMicroelectronics unique “single feature size” strip-based process. The resulting transistor shows extremely high packing density for low on- resistance and low gate charge. Table 1.Device summaryOrder codesMarkingPackagePackaging STD30PF03LT4 D30PF03L DPAK Tape & reel STD30PF03L-1 D30PF03L IPAK Tube January 2008 Rev 2 1/13 www.st.com 13 Document Outline Figure 1. Internal schematic diagram Table 1. Device summary 1 Electrical ratings Table 2. Absolute maximum ratings Table 3. Thermal data 2 Electrical characteristics Table 4. On/off states Table 5. Dynamic Table 6. Switching times Table 7. Source drain diode 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Transconductance Figure 7. Static drain-source on resistance Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations Figure 10. Normalized gate threshold voltage vs temperature Figure 11. Normalized on resistance vs temperature Figure 12. Source-drain diode forward characteristics Figure 13. Normalized breakdown voltage vs temperature 3 Test circuit Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit Figure 16. Test circuit for diode recovery behavior 4 Package mechanical data 5 Packaging mechanical data 6 Revision history Table 8. Document revision history
