Datasheet LTC4332 (Analog Devices) - 10

LTC4332
TIMING DIAGRAM
4332 F07 4332 F05 VE t BUF:SLA 4332 F06 VE t WIDTH t ON_LOW t SCKRSS:SLA L 0.5 V ACTIVE t REM_READY
iming Specifications iming
VE VE VE Y L L
Startup
t SCKL:SLA t DELA t HMISO:SLA 0.8 V 0.2 V t DMISO:SLA
Local Side SPI T oltage Levels for T Figure 6.
ACTIVE VE L VE
Figure 7.
0.2 V
Logic I/O V
t HMOSI:SLA t READY t SCKH:SLA
Figure 5.
Y ON VE SSC L L LINK SSC SS1 t DELA , OR 0.8 V 0.2 V VE , SS3 L t SSFSCK:SLA , SS2 0.8 V LOCAL SIDE t SMOSI:SLA SS11 1 SSx SCK SCK MOSI MISO (CPOL = 0, CPHA = 0) (CPOL = 1, CPHA = 1) Rev. A 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Switching Characteristics Typical Performance Characteristics Pin Functions Block Diagram Test Circuits Timing Diagram Applications Information Package Description Typical Application Related Parts