LT8613 PIN FUNCTIONS SYNC (Pin 1): External Clock Synchronization Input. GND (Pins 11, 12, 13, 14): It is recommended that Ground this pin for low ripple Burst Mode operation at these be connected to GND so that the exposed pad low output loads. Tie to a clock source for synchroniza- GND can be run to the top level GND copper to enhance tion to an external frequency. Apply a DC voltage of 3V or thermal performance. higher or tie to INTVCC for pulse-skipping mode. When SW (Pins 15–19): The SW pins are the outputs of the in pulse-skipping mode, the IQ will increase to several internal power switches. Tie these pins together and con- hundred µA. When SYNC is DC high or synchronized, nect them to the inductor and boost capacitor. This node frequency foldback will be disabled. Do not float this pin. should be kept small on the PCB for good performance. TR/SS (Pin 2): Output Tracking and Soft-Start Pin. This BST (Pin 20): This pin is used to provide a drive voltage, pin allows user control of output voltage ramp rate during higher than the input voltage, to the topside power switch. start-up. A TR/SS voltage below 0.97V forces the LT8613 Place a 0.1µF boost capacitor as close as possible to to regulate the FB pin to equal the TR/SS pin voltage. When the IC. TR/SS is above 0.97V, the tracking function is disabled and the internal reference resumes control of the error ampli- INTVCC (Pin 21): Internal 3.4V Regulator Bypass Pin. fier. An internal 2.2μA pull-up current from INTVCC on this The internal power drivers and control circuits are pow- pin al ows a capacitor to program output voltage slew rate. ered from this voltage. INTVCC maximum output cur- This pin is pulled to ground with an internal 230Ω MOSFET rent is 20mA. Do not load the INTVCC pin with external during shutdown and fault conditions; use a series resistor circuitry. INTVCC current will be supplied from BIAS if if driving from a low impedance output. This pin may be VBIAS > 3.1V, otherwise current will be drawn from VIN. left floating if the tracking function is not needed. Voltage on INTVCC will vary between 2.8V and 3.4V when V RT (Pin 3): A resistor is tied between RT and ground to BIAS is between 3.0V and 3.6V. Decouple this pin to power ground with at least a 1μF low ESR ceramic capac- set the switching frequency. itor placed close to the IC. EN/UV (Pin 4): The LT8613 is shut down when this pin BIAS (Pin 22): The internal regulator will draw current is low and active when this pin is high. The hysteretic from BIAS instead of V threshold voltage is 1.00V going up and 0.96V going IN when BIAS is tied to a voltage higher than 3.1V. For output voltages of 3.3V and above down. Tie to VIN if the shutdown feature is not used. An this pin should be tied to V external resistor divider from V OUT. If this pin is tied to a IN can be used to program supply other than V a V OUT use a 1µF local bypass capacitor IN threshold below which the LT8613 will shut down. on this pin. VIN (Pins 5, 6, 7): The VIN pins supply current to the PG (Pin 23): The PG pin is the open-drain output of an LT8613 internal circuitry and to the internal topside power internal comparator. PG remains low until the FB pin is switch. These pins must be tied together and be locally within ±9% of the final regulation voltage, and there are bypassed. Be sure to place the positive terminal of the no fault conditions. PG is valid when V input capacitor as close as possible to the V IN is above 3.4V, IN pins, and regardless of EN/UV pin state. the negative capacitor terminal as close as possible to the PGND pins. FB (Pin 24): The LT8613 regulates the FB pin to 0.970V. Connect the feedback resistor divider tap to this pin. Also, PGND (Pins 8, 9, 10): Power Switch Ground. These pins connect a phase lead capacitor between FB and V are the return path of the internal bottom-side power OUT. Typically, this capacitor is 4.7pF to 10pF. switch and must be tied together. Place the negative ter- minal of the input capacitor as close to the PGND pins as possible. Rev. A For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
