AD744 Figure 10. Open-Loop Gain and Figure 11. Open Loop Gain and Figure 12. Open-Loop Gain vs. Phase Margin vs. Frequency Phase Margin vs. Frequency Supply Voltage CCOMP = 0 pF CCOMP = 25 pF Figure 13. Common-Mode and Figure 14. Large Signal Frequency Figure 15. Output Swing and Error Power Supply Rejection vs. Response vs. Settling Time Frequency Figure 16. Total Harmonic Distortion Figure 17. Input Noise Voltage Figure 18. Slew Rate vs. Input vs. Frequency, Circuit of Figure 20 Spectral Density Error Signal (G = 10) REV. D –5– Document Outline FEATURES ac Performance dc Performance APPLICATIONS CONNECTION DIAGRAMS PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS METALIZATION PHOTOGRAPH TYPICAL CHARACTERISITICS POWER SUPPLY BYPASSING MEASURING AD744 SETTLING TIME EXTERNAL FREQUENCY COMPENSATION Using Decompensation to Extend the Gain Bandwidth Product HIGH-SPEED OP AMP APPLICATIONS TECHNIQUES DAC Buffers (I-to-V Converters) A HIGH-SPEED, 3 OP AMP INSTRUMENTATION AMPLIFIER CIRCUIT Minimizing Settling Time in Real-World Applications OUTLINE DIMENSIONS ORDERING GUIDE REVISION HISTORY
