Datasheet ADL8111 (Analog Devices) - 8

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ADL8111 Data Sheet 0 0 +85°C +85°C –5 +25°C –5 +25°C –40°C B) –40°C B) d d ( ( S S S S O O –10 –10 URN L URN L T T –15 RE –15 RE UT UT P INP UT O –20 –20 –25 –25 0 1 2 3 4 5 6 7 8
017
0 1 2 3 4 5 6 7 8
020
FREQUENCY (GHz)
20106-
FREQUENCY (GHz)
20106- Figure 16. Input Return Loss Over Temperature vs. Frequency, Figure 19. Output Return Loss Over Temperature vs. Frequency, State = External Bypass A, Path = RFIN to OUT_A (Refer to Figure 75 for the State = External Bypass A, Path = IN_A to RFOUT (Refer to Figure 75 for the Test Circuit) Test Circuit)
0 0 +85°C +85°C ) ) –5 +25°C –5 +25°C dB –40°C dB –40°C ( ( S S LOS –10 LOS N –10 N R R TU TU E E R R –15 –15 TE TE TA TA OFF S –20 OFF S –20 –25 –25 0 1 2 3 4 5 6 7 8
018
0 1 2 3 4 5 6 7 8
021
FREQUENCY (GHz)
20106-
FREQUENCY (GHz)
20106- Figure 17. Off State Return Loss vs. Frequency Over Temperature, Figure 20. Off State Return Loss vs. Frequency Over Temperature, State = External Bypass A, Path = OUT_B (Refer to Figure 75 for the Test State = External Bypass A, Path = IN_B (Refer to Figure 75 for the Test Circuit) Circuit)
0 0 RFIN TO OUT_B +85°C RFIN TO RFOUT +85°C –10 RFIN TO OUT_B +25°C –10 RFIN TO RFOUT +25°C RFIN TO OUT_B –40°C RFIN TO RFOUT –40°C –20 –20 ) ) –30 dB –30 dB ( ( –40 TION –40 TION OLA –50 OLA –50 IS IS –60 –60 –70 –70 –80 –80 0 1 2 3 4 5 6 7 8
019
0 1 2 3 4 5 6 7 8
022
FREQUENCY (GHz)
20106-
FREQUENCY (GHz)
20106- Figure 18. Isolation vs. Frequency Over Temperature, Figure 21. Isolation vs. Frequency Over Temperature, State = External Bypass A (Refer to Figure 75 for the Test Circuit) State = External Bypass A (Refer to Figure 75 for the Test Circuit) Rev. 0 | Page 8 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE POWER DERATING CURVES ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS EXTERNAL BYPASS A STATE INTERNAL AMPLIFIER STATE INTERNAL BYPASS STATE EXTERNAL BYPASS B STATE TEST CIRCUITS THEORY OF OPERATION SIGNAL PATH STATES FOR DIGITAL CONTROL INPUTS APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING During Power-Up During Power-Down EVALUATION PCB EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE