link to page 16 ADL5521Data SheetPIN CONFIGURATION AND FUNCTION DESCRIPTIONSVBIAS 18 VPOSRFIN 27 RFOUTADL5521NIC 3TOP VIEW(Not to Scale)6 NICNIC 45 NICNOTES1. NIC = NO INTERNAL CONNECTION. DONOT CONNECT TO THIS PIN. 002 2. CONNECT THE EXPOSED PAD TO A LOWIMPEDANCE GROUND PLANE. 06828- Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No.MnemonicDescription 1 VBIAS Internal DC Bias. This pin should be connected to VPOS through the R1 resistor. 2 RFIN RF Input. This is the input to the LNA. 3, 4, 5, 6 NC No Connection. No internal connection. 7 RFOUT RF Output. 8 VPOS Supply Voltage. DC bias needs to be bypassed to ground using a low inductance capacitor. This pin is also used for output matching. See the Basic Connections section. 9 (EPAD) Exposed Pad (EPAD) GND. Connect the exposed pad to a low impedance ground plane. Rev. C | Page 6 of 24 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DC SPECIFICATIONS DE-EMBEDDED S-PARAMETERS, VPOS = 3 V TO 5 V, RFIN = PORT 1, VPOS = PORT 2, RFOUT = PORT 3 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 900 MHz, VPOS = 5 V 1950 MHz, VPOS = 5 V 2600 MHZ, VPOS = 5 V 3500 MHz, VPOS = 5 V 900 MHz, VPOS = 3 V 1950 MHz, VPOS = 3 V 2600 MHZ, VPOS = 3 V 3500 MHZ, VPOS = 3 V DC CHARACTERISTICS BASIC CONNECTIONS EVALUATION BOARD SOLDERING INFORMATION AND RECOMMENDED PCB LAND PATTERN TUNING THE ADL5521 FOR OPTIMAL NOISE FIGURE TUNING S22 TUNING THE LNA INPUT FOR OPTIMAL GAIN TUNING THE LNA INPUT FOR OPTIMAL NOISE FIGURE S11 OF THE LNA WITH S22 MATCHED OUTLINE DIMENSIONS ORDERING GUIDE
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