Datasheet ADPA7006CHIP (Analog Devices) - 8

ADPA7006CHIP Data Sheet 0 0 +85°C 700mA –5 +25°C 800mA –5 B) –55°C B) 900mA (d (d S S S S O O –10 –10 L URN L URN T T –15 RE –15 RE UT UT P P IN UT O –20 –20 –25 –25 18 20 22 24 26 28 30 32 34 36 38 40 42 44
-016
18 20 22 24 26 28 30 32 34 36 38 40 42 44
-019
FREQUENCY (GHz)
186
FREQUENCY (GHz)
186 20 20 Figure 16. Input Return Loss vs. Frequency for Various IDQ Values, VDD = 5 V Figure 19. Output Return Loss vs. Frequency for Various Temperatures, VDD = 5 V, IDQ = 800 mA
0 0 5V –5 4V 700mA –5 B) B) 800mA 900mA (d S (d –10 S S S O O –10 URN L –15 T URN L T RE RE –15 UT –20 P UT P UT UT O O –20 –25 –30 –25 18 20 22 24 26 28 30 32 34 36 38 40 42 44
-017
18 20 22 24 26 28 30 32 34 36 38 40 42 44
-020
FREQUENCY (GHz)
186 186 20
FREQUENCY (GHz)
20 Figure 17. Output Return Loss vs Frequency for Various Supply Voltages Figure 20. Output Return Loss vs. Frequency for Various Supply Currents (IDQ), (VDD), IDQ = 800 mA VDD = 5 V
0 12 –10 +85°C +25°C 10 ) –55°C B –20 (d N B) 8 d IO ( T –30 A L URE O 6 S IG –40 F E SE I IS O +85°C 4 N +25°C –50 EVER –55°C R –60 2 –70 0 18 20 22 24 26 28 30 32 34 36 38 40 42 44
-018
18 20 22 24 26 28 30 32 34 36 38 40 42 44
-021
FREQUENCY (GHz)
186 186 20
FREQUENCY (GHz)
20 Figure 18. Reverse Isolation vs. Frequency for Various Temperatures, Figure 21. Noise Figure vs. Frequency for Various Temperatures, VDD = 5 V, VDD = 5 V, IDQ = 800 mA IDQ = 800 mA Rev. 0 | Page 8 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 18 GHz TO 20 GHz FREQUENCY RANGE 20 GHz TO 28 GHz FREQUENCY RANGE 28 GHz TO 36 GHz FREQUENCY RANGE 36 GHz TO 44 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTIC CONSTANT DRAIN CURRENT (IDD) OPERATION THEORY OF OPERATION APPLICATIONS INFORMATION MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Handling Precautions Mounting Wire Bonding BIASING THE ADPA7006CHIP WITH THE HMC980LP4E APPLICATION CIRCUIT SETUP LIMITING VGATE FOR THE ADPA7006CHIP VGGx AMR (ABSOLUTE MAXIMUM RATING) REQUIREMENT HMC980LP4E BIAS SEQUENCE Power-Up Sequence Power-Down Sequence CONSTANT DRAIN CURRENT BIASING vs. CONSTANT GATE VOLTAGE BIASING TYPICAL APPLICATION CIRCUIT ASSEMBLY DIAGRAMS OUTLINE DIMENSIONS ORDERING GUIDE