Datasheet ADPA7005CHIP (Analog Devices) - 3

Data Sheet ADPA7005CHIP SPECIFICATIONS 20 GHz TO 34 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, and quiescent supply current (IDQ) = 1200 mA for nominal operation, unless otherwise noted.
Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 20 34 GHz GAIN 15 17 dB Gain Flatness ±0.5 dB Gain Variation Over Temperature 0.012 dB/°C NOISE FIGURE 7 dB RETURN LOSS Input 18 dB Output 20 dB OUTPUT Output Power for 1 dB Compression P1dB 28 31 dBm Saturated Output Power PSAT 32 dBm Output Third-Order Intercept IP3 41 dBm Measurement taken at output power (POUT) per tone = 14 dBm SUPPLY Current IDQ 1200 mA Adjust the gate bias voltage (VGG1) between −1.5 V up to 0 V to achieve the desired IDQ Voltage VDD 4 5 V
34 GHz TO 44 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, and IDQ = 1200 mA for nominal operation, unless otherwise noted.
Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 34 44 GHz GAIN 11.5 14.5 dB Gain Flatness ±0.7 dB Gain Variation Over Temperature 0.024 dB/°C NOISE FIGURE 6 dB RETURN LOSS Input 15 dB Output 17 dB OUTPUT Output Power for 1 dB Compression P1dB 27 30 dBm Saturated Output Power PSAT 31 dBm Output Third-Order Intercept IP3 40.5 dBm Measurement taken at POUT per tone = 14 dBm SUPPLY Current IDQ 1200 mA Adjust VGG1 between −1.5 V up to 0 V to achieve the desired IDQ Voltage VDD 4 5 V Rev. 0 | Page 3 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 20 GHz TO 34 GHz FREQUENCY RANGE 34 GHz TO 44 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTIC CONSTANT IDD OPERATION THEORY OF OPERATION APPLICATIONS INFORMATION MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Handling Precautions Mounting Wire Bonding BIASING ADPA7005CHIP WITH THE HMC980LP4E APPLICATION CIRCUIT SETUP LIMITING VGATE FOR ADPA7005CHIP VGGx ABSOLUTE MAXIMUM RATING REQUIREMENT HMC980LP4E BIAS SEQUENCE Power-Up Sequence Power-Down Sequence CONSTANT DRAIN CURRENT BIASING vs. CONSTANT GATE VOLTAGE BIASING TYPICAL APPLICATION CIRCUIT ASSEMBLY DIAGRAM OUTLINE DIMENSIONS ORDERING GUIDE