Data SheetHMC8205BCHIPSABSOLUTE MAXIMUM RATINGSTHERMAL RESISTANCETable 4. ParameterRating Thermal performance is directly linked to mounting substrate Drain Bias Voltage (V design and operating environment. Careful attention to DDx)
60 V dc Gate Bias Voltage (V thermal design is required. GG1) −8 V dc to 0 V dc Radio Frequency Input Power (RFIN) 35 dBm θJC is the junction to case thermal resistance, channel to bottom Continuous Power Dissipation (PDISS), T = 85°C 115.7 W of die. (Derate 826 mW/°C Above 85°C) Storage Temperature Range −65°C to +150°C Table 5. Thermal Resistance Operating Temperature Range −55°C to +85°C Package TypeθJCUnit Electrostatic Discharge (ESD) Sensitivity C-5-7 1.21 °C/W Human Body Model (HBM) Class 1A, Passed 375 V Table 6. Reliability Information Stresses at or above those listed under Absolute Maximum Temperature Ratings may cause permanent damage to the product. This is a Parameter(°C) stress rating only; functional operation of the product at these Junction Temperature to Maintain 225 1,000,000 Hour Mean Time to Failure (MTTF) or any other conditions above those indicated in the Nominal Junction Temperature (T = 85°C, 163.7 operational section of this specification is not implied. VDD = 50 V, IDQ = 1300 mA) Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. A | Page 5 of 19 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTION INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Handling Precautions TYPICAL APPLICATION CIRCUIT ASSEMBLY DIAGRAM OUTLINE DIMENSIONS ORDERING GUIDE
