link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 Data SheetHMC1114PIN CONFIGURATION AND FUNCTION DESCRIPTIONSND NDND NDNDG G V DD1 G G V DD2 V DD2 G 32 31 30 29 28 27 26 25GND 124 GNDGND 223 GNDGND 322 GNDRFIN 4HMC111421 RFOUTRFIN 5TOP VIEW20 RFOUT(Not to Scale)GND 619 GNDGND 718 GNDGND 817 GND9 10 11 12 13 14 15 16 NDND NDND ND NDG V GG1 G G V GG2 G G GNOTES 002 1. EXPOSED PAD. EXPOSED PAD MUSTBE CONNECTED TO RF/DC GROUND. 13530- Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No.Mnemonic Description 1 to 3, 6 to 9, 11, 12, 14 to GND Ground. These pins and the package bottom (EPAD) must be connected to RF/dc ground. See 19, 22 to 25, 28, 29, 31, 32 Figure 3 for the GND interface schematic. 4, 5 RFIN RF Input. These pins are dc-coupled and matched to 50 Ω. See Figure 4 for the RFIN interface schematic. 10, 13 VGG1, VGG2 Gate Control Voltage Pins. External bypass capacitors of 1 μF and 10 μF are required. See Figure 5 for the VGG1 and VGG2 interface schematic. 20, 21 RFOUT RF Output. These pins are ac-coupled and matched to 50 Ω. See Figure 6 for the RFOUT interface schematic. 26, 27, 30 VDD1, VDD2 Drain Bias Pins for the Amplifier. External bypass capacitors of 100 pF, 1 μF, and 10 μF are required. See Figure 7 for the VDD1 and VDD2 interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground. INTERFACE SCHEMATICSGND 003 RFOUT 006 13530- 13530- Figure 3. GND Interface Figure 6. RFOUT Interface VDD1, VDD2RFIN 007 004 13530- 13530- Figure 4. RFIN Interface Figure 7. VDD1 and VDD2 Interface VGG1, VGG2 005 13530- Figure 5. VGG1 and VGG2 Interface Rev. A | Page 5 of 15 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS TOTAL SUPPLY CURRENT BY VDD ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCE During Power-Up During Power-Down TYPICAL APPLICATION CIRCUIT EVALUATION PRINTED CIRCUIT BOARD (PCB) BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE
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