Datasheet HMC637ASCPZ-EP (Analog Devices) - 9

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Enhanced Product HMC637ASCPZ-EP OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 5.10 0.30 5.00 SQ 0.25 PIN 1 P IN 1 4.90 INDICATOR 0.20 IN D IC AT O R AR E A OP T IO N S (SEE DETAIL A) AREA 25 32 24 1 0.50 3.80 BSC EXPOSED 3.70 SQ PAD 3.60 17 8 16 9 0.45 TOP VIEW BOTTOM VIEW 0.20 MIN 0.40 0.35 3.50 REF 0.80 0.75 SIDE VIEW FOR PROPER CONNECTION OF 0.05 MAX 0.70 THE EXPOSED PAD, REFER TO 0.02 NOM THE PIN CONFIGURATION AND COPLANARITY FUNCTION DESCRIPTIONS SEATING 0.08 SECTION OF THIS DATA SHEET. PLANE 0.203 REF A 2018- -005168 12- G K P COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-4 09-
Figure 18. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm and 0.75 mm Package Height (CP-32-29) Dimensions shown in millimeters
ORDERING GUIDE Model1 Temperature Range MSL Rating2 Package Description Package Option
HMC637ASCPZ-EP-PT −55°C to +105°C MSL3 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-29 HMC637ASCPZ-EP-R7 −55°C to +105°C MSL3 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-29 1 The HMC637ASCPZ-EP is RoHS compliant. 2 See the Absolute Maximum Ratings section for additional information.
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Rev. 0 | Page 9 of 9 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE POWER DERATING CURVES ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE